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REJ09B0028-0500
The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.
16
H8/3694N H8/3694F H8/3694 H8/3693 H8/3692 H8/3691 H8/3690
H8/3694Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series HD64N3694G, HD64F3694, HD6433694, HD6433693, HD6433692, HD6433691, HD6433690, HD6483694G, HD64F3694G, HD6433694G, HD6433693G, HD6433692G, HD6433691G, HD6433690G
Rev.5.00 Revision Date: Nov. 02, 2005
Rev.5.00 Nov. 02, 2005 Page ii of xxviii
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
Rev.5.00 Nov. 02, 2005 Page iii of xxviii
General Precautions on Handling of Product
1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed.
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Configuration of This Manual
This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index
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Preface
The H8/3694 Group are single-chip microcomputers made up of the high-speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible with the H8/300 CPU. Target Users: This manual was written for users who will be using the H8/3694 Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8/3694 Group to the target users. Refer to the H8/300H Series Software Manual for a detailed description of the instruction set.
Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the H8/300H Series Software Manual. * In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 20, List of Registers. Example: Bit order: The MSB is on the left and the LSB is on the right. Notes: When using the on-chip emulator (E7, E8) for H8/3694 program development and debugging, the following restrictions must be noted. 1. The NMI pin is reserved for the E7 or E8, and cannot be used. 2. Pins P85, P86, and P87 cannot be used. In order to use these pins, additional hardware must be provided on the user board. 3. Area H'7000 to H'7FFF is used by the E7 or E8, and is not available to the user. 4. Area H'F780 to H'FB7F must on no account be accessed.
Rev.5.00 Nov. 02, 2005 Page vi of xxviii
5. When the E7 or E8 is used, address breaks can be set as either available to the user or for use by the E7 or E8. If address breaks are set as being used by the E7 or E8, the address break control registers must not be accessed. 6. When the E7 or E8 is used, NMI is an input/output pin (open-drain in output mode), P85 and P87 are input pins, and P86 is an output pin. Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/
H8/3694 Group manuals:
Document Title H8/3694 Group Hardware Manual H8/300H Series Software Manual Document No. This manual REJ09B0213
User's manuals for development tools:
Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual Microcomputer Development Environment System H8S, H8/300 Series Simulator/Debugger User's Manual H8S, H8/300 Series High-Performance Embedded Workshop 3, Tutorial H8S, H8/300 Series High-Performance Embedded Workshop 3, User's Manual Document No. REJ10B0058 ADE-702-282 REJ10B0024 REJ10B0026
Application notes:
Document Title H8S, H8/300 Series C/C++ Compiler Package Application Note Single Power Supply F-ZTAT On-Board Programming
TM
Document No. REJ05B0464 ADE-502-055
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Contents
Section 1 Overview................................................................................................1
1.1 1.2 1.3 1.4 Features.................................................................................................................................. 1 Internal Block Diagram.......................................................................................................... 4 Pin Arrangement .................................................................................................................... 6 Pin Functions ......................................................................................................................... 9
Section 2 CPU......................................................................................................13
2.1 2.2 Address Space and Memory Map ........................................................................................ 14 Register Configuration......................................................................................................... 17 2.2.1 General Registers.................................................................................................... 18 2.2.2 Program Counter (PC) ............................................................................................ 19 2.2.3 Condition-Code Register (CCR)............................................................................. 19 Data Formats........................................................................................................................ 21 2.3.1 General Register Data Formats ............................................................................... 21 2.3.2 Memory Data Formats ............................................................................................ 23 Instruction Set ...................................................................................................................... 24 2.4.1 Table of Instructions Classified by Function .......................................................... 24 2.4.2 Basic Instruction Formats ....................................................................................... 33 Addressing Modes and Effective Address Calculation........................................................ 34 2.5.1 Addressing Modes .................................................................................................. 34 2.5.2 Effective Address Calculation ................................................................................ 38 Basic Bus Cycle ................................................................................................................... 40 2.6.1 Access to On-Chip Memory (RAM, ROM)............................................................ 40 2.6.2 On-Chip Peripheral Modules .................................................................................. 41 CPU States ........................................................................................................................... 42 Usage Notes ......................................................................................................................... 43 2.8.1 Notes on Data Access to Empty Areas ................................................................... 43 2.8.2 EEPMOV Instruction.............................................................................................. 43 2.8.3 Bit Manipulation Instruction................................................................................... 43
2.3
2.4
2.5
2.6
2.7 2.8
Section 3 Exception Handling .............................................................................49
3.1 3.2 Exception Sources and Vector Address ............................................................................... 49 Register Descriptions ........................................................................................................... 51 3.2.1 Interrupt Edge Select Register 1 (IEGR1) .............................................................. 51 3.2.2 Interrupt Edge Select Register 2 (IEGR2) .............................................................. 52 3.2.3 Interrupt Enable Register 1 (IENR1) ...................................................................... 53 3.2.4 Interrupt Flag Register 1 (IRR1)............................................................................. 54
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3.3 3.4
3.5
3.2.5 Wakeup Interrupt Flag Register (IWPR) ................................................................ 55 Reset Exception Handling.................................................................................................... 56 Interrupt Exception Handling .............................................................................................. 57 3.4.1 External Interrupts .................................................................................................. 57 3.4.2 Internal Interrupts ................................................................................................... 58 3.4.3 Interrupt Handling Sequence .................................................................................. 58 3.4.4 Interrupt Response Time......................................................................................... 60 Usage Notes ......................................................................................................................... 62 3.5.1 Interrupts after Reset............................................................................................... 62 3.5.2 Notes on Stack Area Use ........................................................................................ 62 3.5.3 Notes on Rewriting Port Mode Registers ............................................................... 62
Section 4 Address Break ..................................................................................... 63
4.1 Register Descriptions........................................................................................................... 63 4.1.1 Address Break Control Register (ABRKCR) ......................................................... 64 4.1.2 Address Break Status Register (ABRKSR) ............................................................ 65 4.1.3 Break Address Registers (BARH, BARL).............................................................. 66 4.1.4 Break Data Registers (BDRH, BDRL) ................................................................... 66 Operation ............................................................................................................................. 66
4.2
Section 5 Clock Pulse Generators ....................................................................... 69
5.1 System Clock Generator ...................................................................................................... 70 5.1.1 Connecting Crystal Resonator ................................................................................ 70 5.1.2 Connecting Ceramic Resonator .............................................................................. 71 5.1.3 External Clock Input Method ................................................................................. 71 Subclock Generator.............................................................................................................. 72 5.2.1 Connecting 32.768-kHz Crystal Resonator ............................................................ 72 5.2.2 Pin Connection when Not Using Subclock............................................................. 73 Prescalers ............................................................................................................................. 73 5.3.1 Prescaler S .............................................................................................................. 73 5.3.2 Prescaler W............................................................................................................. 73 Usage Notes ......................................................................................................................... 74 5.4.1 Note on Resonators................................................................................................. 74 5.4.2 Notes on Board Design ........................................................................................... 74
5.2
5.3
5.4
Section 6 Power-Down Modes............................................................................ 75
6.1 Register Descriptions........................................................................................................... 75 6.1.1 System Control Register 1 (SYSCR1) .................................................................... 76 6.1.2 System Control Register 2 (SYSCR2) .................................................................... 78 6.1.3 Module Standby Control Register 1 (MSTCR1) .................................................... 79
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6.2
6.3 6.4
6.5
Mode Transitions and States of LSI..................................................................................... 80 6.2.1 Sleep Mode ............................................................................................................. 83 6.2.2 Standby Mode ......................................................................................................... 83 6.2.3 Subsleep Mode........................................................................................................ 83 6.2.4 Subactive Mode ...................................................................................................... 84 Operating Frequency in Active Mode.................................................................................. 84 Direct Transition .................................................................................................................. 85 6.4.1 Direct Transition from Active Mode to Subactive Mode ....................................... 85 6.4.2 Direct Transition from Subactive Mode to Active Mode ....................................... 85 Module Standby Function.................................................................................................... 86
Section 7 ROM ....................................................................................................87
7.1 7.2 Block Configuration............................................................................................................. 87 Register Descriptions ........................................................................................................... 88 7.2.1 Flash Memory Control Register 1 (FLMCR1)........................................................ 89 7.2.2 Flash Memory Control Register 2 (FLMCR2)........................................................ 90 7.2.3 Erase Block Register 1 (EBR1) .............................................................................. 91 7.2.4 Flash Memory Power Control Register (FLPWCR) ............................................... 92 7.2.5 Flash Memory Enable Register (FENR) ................................................................. 92 On-Board Programming Modes........................................................................................... 93 7.3.1 Boot Mode .............................................................................................................. 93 7.3.2 Programming/Erasing in User Program Mode........................................................ 96 Flash Memory Programming/Erasing .................................................................................. 98 7.4.1 Program/Program-Verify ........................................................................................ 98 7.4.2 Erase/Erase-Verify................................................................................................ 100 7.4.3 Interrupt Handling when Programming/Erasing Flash Memory........................... 101 Program/Erase Protection .................................................................................................. 103 7.5.1 Hardware Protection ............................................................................................. 103 7.5.2 Software Protection............................................................................................... 103 7.5.3 Error Protection..................................................................................................... 103 Programmer Mode ............................................................................................................. 104 Power-Down States for Flash Memory.............................................................................. 104
7.3
7.4
7.5
7.6 7.7
Section 8 RAM ..................................................................................................107 Section 9 I/O Ports .............................................................................................109
9.1 Port 1.................................................................................................................................. 109 9.1.1 Port Mode Register 1 (PMR1) .............................................................................. 110 9.1.2 Port Control Register 1 (PCR1) ............................................................................ 111 9.1.3 Port Data Register 1 (PDR1)................................................................................. 111
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9.2
9.3
9.4
9.5
9.6
9.1.4 Port Pull-Up Control Register 1 (PUCR1)............................................................ 112 9.1.5 Pin Functions ........................................................................................................ 112 Port 2.................................................................................................................................. 114 9.2.1 Port Control Register 2 (PCR2) ............................................................................ 115 9.2.2 Port Data Register 2 (PDR2) ................................................................................ 115 9.2.3 Pin Functions ........................................................................................................ 116 Port 5.................................................................................................................................. 117 9.3.1 Port Mode Register 5 (PMR5) .............................................................................. 118 9.3.2 Port Control Register 5 (PCR5) ............................................................................ 119 9.3.3 Port Data Register 5 (PDR5) ................................................................................ 119 9.3.4 Port Pull-Up Control Register 5 (PUCR5)............................................................ 120 9.3.5 Pin Functions ........................................................................................................ 120 Port 7.................................................................................................................................. 123 9.4.1 Port Control Register 7 (PCR7) ............................................................................ 124 9.4.2 Port Data Register 7 (PDR7) ................................................................................ 124 9.4.3 Pin Functions ........................................................................................................ 125 Port 8.................................................................................................................................. 126 9.5.1 Port Control Register 8 (PCR8) ............................................................................ 126 9.5.2 Port Data Register 8 (PDR8) ................................................................................ 127 9.5.3 Pin Functions ........................................................................................................ 127 Port B ................................................................................................................................. 130 9.6.1 Port Data Register B (PDRB) ............................................................................... 130
Section 10 Timer A ........................................................................................... 131
10.1 Features.............................................................................................................................. 131 10.2 Input/Output Pins............................................................................................................... 132 10.3 Register Descriptions......................................................................................................... 133 10.3.1 Timer Mode Register A (TMA)............................................................................ 133 10.3.2 Timer Counter A (TCA) ....................................................................................... 134 10.4 Operation ........................................................................................................................... 135 10.4.1 Interval Timer Operation ...................................................................................... 135 10.4.2 Clock Time Base Operation.................................................................................. 135 10.4.3 Clock Output......................................................................................................... 135 10.5 Usage Note......................................................................................................................... 135
Section 11 Timer V ........................................................................................... 137
11.1 Features.............................................................................................................................. 137 11.2 Input/Output Pins............................................................................................................... 138 11.3 Register Descriptions......................................................................................................... 139 11.3.1 Timer Counter V (TCNTV).................................................................................. 139
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11.3.2 Time Constant Registers A and B (TCORA, TCORB) ........................................ 139 11.3.3 Timer Control Register V0 (TCRV0) ................................................................... 140 11.3.4 Timer Control/Status Register V (TCSRV) .......................................................... 142 11.3.5 Timer Control Register V1 (TCRV1) ................................................................... 143 11.4 Operation ........................................................................................................................... 144 11.4.1 Timer V Operation................................................................................................ 144 11.5 Timer V Application Examples ......................................................................................... 148 11.5.1 Pulse Output with Arbitrary Duty Cycle............................................................... 148 11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input .............. 149 11.6 Usage Notes ....................................................................................................................... 150
Section 12 Timer W ...........................................................................................153
12.1 Features.............................................................................................................................. 153 12.2 Input/Output Pins ............................................................................................................... 156 12.3 Register Descriptions ......................................................................................................... 156 12.3.1 Timer Mode Register W (TMRW) ....................................................................... 157 12.3.2 Timer Control Register W (TCRW) ..................................................................... 158 12.3.3 Timer Interrupt Enable Register W (TIERW) ...................................................... 159 12.3.4 Timer Status Register W (TSRW) ........................................................................ 160 12.3.5 Timer I/O Control Register 0 (TIOR0) ................................................................. 161 12.3.6 Timer I/O Control Register 1 (TIOR1) ................................................................. 163 12.3.7 Timer Counter (TCNT)......................................................................................... 164 12.3.8 General Registers A to D (GRA to GRD)............................................................. 164 12.4 Operation ........................................................................................................................... 165 12.4.1 Normal Operation ................................................................................................. 165 12.4.2 PWM Operation.................................................................................................... 169 12.5 Operation Timing............................................................................................................... 174 12.5.1 TCNT Count Timing ............................................................................................ 174 12.5.2 Output Compare Output Timing ........................................................................... 174 12.5.3 Input Capture Timing............................................................................................ 175 12.5.4 Timing of Counter Clearing by Compare Match .................................................. 176 12.5.5 Buffer Operation Timing ...................................................................................... 176 12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match.................................. 177 12.5.7 Timing of IMFA to IMFD Setting at Input Capture ............................................. 178 12.5.8 Timing of Status Flag Clearing............................................................................. 178 12.6 Usage Notes ....................................................................................................................... 179
Section 13 Watchdog Timer ..............................................................................183
13.1 Features.............................................................................................................................. 183 13.2 Register Descriptions ......................................................................................................... 184
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13.2.1 Timer Control/Status Register WD (TCSRWD) .................................................. 184 13.2.2 Timer Counter WD (TCWD)................................................................................ 185 13.2.3 Timer Mode Register WD (TMWD) .................................................................... 186 13.3 Operation ........................................................................................................................... 187
Section 14 Serial Communication Interface 3 (SCI3)....................................... 189
14.1 Features.............................................................................................................................. 189 14.2 Input/Output Pins............................................................................................................... 191 14.3 Register Descriptions......................................................................................................... 191 14.3.1 Receive Shift Register (RSR) ............................................................................... 192 14.3.2 Receive Data Register (RDR)............................................................................... 192 14.3.3 Transmit Shift Register (TSR) .............................................................................. 192 14.3.4 Transmit Data Register (TDR).............................................................................. 192 14.3.5 Serial Mode Register (SMR) ................................................................................ 193 14.3.6 Serial Control Register 3 (SCR3) ......................................................................... 194 14.3.7 Serial Status Register (SSR) ................................................................................. 196 14.3.8 Bit Rate Register (BRR) ....................................................................................... 198 14.4 Operation in Asynchronous Mode ..................................................................................... 205 14.4.1 Clock..................................................................................................................... 205 14.4.2 SCI3 Initialization................................................................................................. 206 14.4.3 Data Transmission ................................................................................................ 207 14.4.4 Serial Data Reception ........................................................................................... 209 14.5 Operation in Clocked Synchronous Mode ......................................................................... 213 14.5.1 Clock..................................................................................................................... 213 14.5.2 SCI3 Initialization................................................................................................. 213 14.5.3 Serial Data Transmission ...................................................................................... 214 14.5.4 Serial Data Reception (Clocked Synchronous Mode) .......................................... 217 14.5.5 Simultaneous Serial Data Transmission and Reception........................................ 219 14.6 Multiprocessor Communication Function.......................................................................... 221 14.6.1 Multiprocessor Serial Data Transmission ............................................................. 222 14.6.2 Multiprocessor Serial Data Reception .................................................................. 224 14.7 Interrupts............................................................................................................................ 228 14.8 Usage Notes ....................................................................................................................... 229 14.8.1 Break Detection and Processing ........................................................................... 229 14.8.2 Mark State and Break Sending ............................................................................. 229 14.8.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) ..................................................................... 229 14.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode......................................................................................... 230
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Section 15 I2C Bus Interface 2 (IIC2) ................................................................231
15.1 Features.............................................................................................................................. 231 15.2 Input/Output Pins ............................................................................................................... 233 15.3 Register Descriptions ......................................................................................................... 233 15.3.1 I2C Bus Control Register 1 (ICCR1)..................................................................... 234 15.3.2 I2C Bus Control Register 2 (ICCR2)..................................................................... 236 15.3.3 I2C Bus Mode Register (ICMR)............................................................................ 237 15.3.4 I2C Bus Interrupt Enable Register (ICIER) ........................................................... 239 15.3.5 I2C Bus Status Register (ICSR)............................................................................. 241 15.3.6 Slave Address Register (SAR).............................................................................. 244 15.3.7 I2C Bus Transmit Data Register (ICDRT)............................................................. 245 15.3.8 I2C Bus Receive Data Register (ICDRR).............................................................. 245 15.3.9 I2C Bus Shift Register (ICDRS)............................................................................ 245 15.4 Operation ........................................................................................................................... 246 15.4.1 I2C Bus Format...................................................................................................... 246 15.4.2 Master Transmit Operation ................................................................................... 247 15.4.3 Master Receive Operation..................................................................................... 249 15.4.4 Slave Transmit Operation ..................................................................................... 251 15.4.5 Slave Receive Operation....................................................................................... 253 15.4.6 Clocked Synchronous Serial Format..................................................................... 255 15.4.7 Noise Canceler...................................................................................................... 257 15.4.8 Example of Use..................................................................................................... 258 15.5 Interrupt Request................................................................................................................ 262 15.6 Bit Synchronous Circuit..................................................................................................... 263 15.7 Usage Notes ....................................................................................................................... 264 15.7.1 Issue (Retransmission) of Start/Stop Conditions .................................................. 264 15.7.2 WAIT Setting in I2C Bus Mode Register (ICMR) ................................................ 264
Section 16 A/D Converter..................................................................................265
16.1 Features.............................................................................................................................. 265 16.2 Input/Output Pins ............................................................................................................... 267 16.3 Register Descriptions ......................................................................................................... 268 16.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 268 16.3.2 A/D Control/Status Register (ADCSR) ................................................................ 269 16.3.3 A/D Control Register (ADCR) ............................................................................. 270 16.4 Operation ........................................................................................................................... 271 16.4.1 Single Mode.......................................................................................................... 271 16.4.2 Scan Mode ............................................................................................................ 271 16.4.3 Input Sampling and A/D Conversion Time .......................................................... 272 16.4.4 External Trigger Input Timing.............................................................................. 273
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16.5 A/D Conversion Accuracy Definitions .............................................................................. 274 16.6 Usage Notes ....................................................................................................................... 276 16.6.1 Permissible Signal Source Impedance .................................................................. 276 16.6.2 Influences on Absolute Accuracy ......................................................................... 276
Section 17 EEPROM......................................................................................... 277
17.1 Features.............................................................................................................................. 277 17.2 Input/Output Pins............................................................................................................... 279 17.3 Register Description .......................................................................................................... 279 17.3.1 EEPROM Key Register (EKR)............................................................................. 279 17.4 Operation ........................................................................................................................... 280 17.4.1 EEPROM Interface............................................................................................... 280 17.4.2 Bus Format and Timing ........................................................................................ 280 17.4.3 Start Condition...................................................................................................... 280 17.4.4 Stop Condition ...................................................................................................... 281 17.4.5 Acknowledge ........................................................................................................ 281 17.4.6 Slave Addressing .................................................................................................. 281 17.4.7 Write Operations................................................................................................... 283 17.4.8 Acknowledge Polling............................................................................................ 284 17.4.9 Read Operation ..................................................................................................... 285 17.5 Usage Notes ....................................................................................................................... 288 17.5.1 Data Protection at VCC On/Off............................................................................... 288 17.5.2 Write/Erase Endurance ......................................................................................... 288 17.5.3 Noise Suppression Time ....................................................................................... 288
Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional).. 289
18.1 Features.............................................................................................................................. 289 18.2 Register Descriptions......................................................................................................... 290 18.2.1 Low-Voltage-Detection Control Register (LVDCR)............................................ 290 18.2.2 Low-Voltage-Detection Status Register (LVDSR)............................................... 292 18.3 Operation ........................................................................................................................... 293 18.3.1 Power-On Reset Circuit ........................................................................................ 293 18.3.2 Low-Voltage Detection Circuit............................................................................. 294
Section 19 Power Supply Circuit ...................................................................... 299
19.1 When Using Internal Power Supply Step-Down Circuit ................................................... 299 19.2 When Not Using Internal Power Supply Step-Down Circuit............................................. 300
Section 20 List of Registers............................................................................... 301
20.1 Register Addresses (Address Order).................................................................................. 302
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20.2 Register Bits....................................................................................................................... 307 20.3 Registers States in Each Operating Mode .......................................................................... 311
Section 21 Electrical Characteristics .................................................................315
21.1 Absolute Maximum Ratings .............................................................................................. 315 21.2 Electrical Characteristics (F-ZTATTM Version, EEPROM Stacked F-ZTATTM Version).......................................... 315 21.2.1 Power Supply Voltage and Operating Ranges ...................................................... 315 21.2.2 DC Characteristics ................................................................................................ 318 21.2.3 AC Characteristics ................................................................................................ 324 21.2.4 A/D Converter Characteristics .............................................................................. 328 21.2.5 Watchdog Timer Characteristics........................................................................... 329 21.2.6 Flash Memory Characteristics .............................................................................. 330 21.2.7 EEPROM Characteristics...................................................................................... 332 21.2.8 Power-Supply-Voltage Detection Circuit Characteristics (Optional) ................... 333 21.2.9 Power-On Reset Circuit Characteristics (Optional) .............................................. 334 21.3 Electrical Characteristics (Mask-ROM Version, EEPROM Stacked Mask-ROM Version)....................................... 334 21.3.1 Power Supply Voltage and Operating Ranges ...................................................... 334 21.3.2 DC Characteristics ................................................................................................ 337 21.3.3 AC Characteristics ................................................................................................ 343 21.3.4 A/D Converter Characteristics .............................................................................. 347 21.3.5 Watchdog Timer Characteristics........................................................................... 348 21.3.6 EEPROM Characteristics...................................................................................... 349 21.3.7 Power-Supply-Voltage Detection Circuit Characteristics (Optional) ................... 350 21.3.8 Power-On Reset Circuit Characteristics (Optional) .............................................. 351 21.4 Operation Timing............................................................................................................... 351 21.5 Output Load Condition ...................................................................................................... 354
Appendix A Instruction Set ...............................................................................355
A.1 A.2 A.3 A.4 Instruction List................................................................................................................... 355 Operation Code Map.......................................................................................................... 370 Number of Execution States .............................................................................................. 373 Combinations of Instructions and Addressing Modes ....................................................... 384
Appendix B I/O Port Block Diagrams ...............................................................385
B.1 B.2 I/O Port Block Diagrams.................................................................................................... 385 Port States in Each Operating State ................................................................................... 401
Appendix C Product Code Lineup.....................................................................402
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Appendix D Package Dimensions ..................................................................... 405 Appendix E EEPROM Stacked-Structure Cross-Sectional View ..................... 410 Main Revisions and Additions in this Edition..................................................... 411 Index .................................................................................................................. 415
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Figures
Section 1 Figure 1.1 Figure 1.2 Figure 1.3 Overview Internal Block Diagram of H8/3694 Group of F-ZTATTM and Mask-ROM Versions.. 4 Internal Block Diagram of H8/3694N (EEPROM Stacked Version) ............................ 5 Pin Arrangement of H8/3694 Group of F-ZTATTM and Mask-ROM Versions (FP-64E, FP-64A).......................................................................................................... 6 Figure 1.4 Pin Arrangement of H8/3694 Group of F-ZTATTM and Mask-ROM Versions (FP-48F, FP-48B, TNP-48)............................................................................................ 7 Figure 1.5 Pin Arrangement of H8/3694N (EEPROM Stacked Version) (FP-64E)....................... 8 Section 2 CPU Figure 2.1 Memory Map (1) ......................................................................................................... 14 Figure 2.1 Memory Map (2) ......................................................................................................... 15 Figure 2.1 Memory Map (3) ......................................................................................................... 16 Figure 2.2 CPU Registers ............................................................................................................. 17 Figure 2.3 Usage of General Registers ......................................................................................... 18 Figure 2.4 Relationship between Stack Pointer and Stack Area ................................................... 19 Figure 2.5 General Register Data Formats (1).............................................................................. 21 Figure 2.5 General Register Data Formats (2).............................................................................. 22 Figure 2.6 Memory Data Formats................................................................................................. 23 Figure 2.7 Instruction Formats...................................................................................................... 34 Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 37 Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 40 Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 41 Figure 2.11 CPU Operation States................................................................................................ 42 Figure 2.12 State Transitions ........................................................................................................ 43 Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same Address .. 44 Section 3 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Section 4 Figure 4.1 Figure 4.2 Figure 4.2 Exception Handling Reset Sequence............................................................................................................ 58 Stack Status after Exception Handling ........................................................................ 60 Interrupt Sequence....................................................................................................... 61 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 62 Address Break Block Diagram of Address Break................................................................................ 63 Address Break Interrupt Operation Example (1)......................................................... 67 Address Break Interrupt Operation Example (2)......................................................... 67
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Section 5 Clock Pulse Generators Figure 5.1 Block Diagram of Clock Pulse Generators.................................................................. 69 Figure 5.2 Block Diagram of System Clock Generator ................................................................ 70 Figure 5.3 Typical Connection to Crystal Resonator.................................................................... 70 Figure 5.4 Equivalent Circuit of Crystal Resonator...................................................................... 70 Figure 5.5 Typical Connection to Ceramic Resonator.................................................................. 71 Figure 5.6 Example of External Clock Input ................................................................................ 71 Figure 5.7 Block Diagram of Subclock Generator ....................................................................... 72 Figure 5.8 Typical Connection to 32.768-kHz Crystal Resonator................................................ 72 Figure 5.9 Equivalent Circuit of 32.768-kHz Crystal Resonator.................................................. 72 Figure 5.10 Pin Connection when not Using Subclock ................................................................ 73 Figure 5.11 Example of Incorrect Board Design ........................................................................... 74 Section 6 Power-Down Modes Figure 6.1 Mode Transition Diagram ........................................................................................... 80 Section 7 Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 Section 9 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Figure 9.6 ROM Flash Memory Block Configuration............................................................................ 88 Programming/Erasing Flowchart Example in User Program Mode............................ 97 Program/Program-Verify Flowchart ........................................................................... 99 Erase/Erase-Verify Flowchart ................................................................................... 102 I/O Ports Port 1 Pin Configuration............................................................................................ 109 Port 2 Pin Configuration............................................................................................ 114 Port 5 Pin Configuration............................................................................................ 117 Port 7 Pin Configuration............................................................................................ 123 Port 8 Pin Configuration............................................................................................ 126 Port B Pin Configuration........................................................................................... 130
Section 10 Timer A Figure 10.1 Block Diagram of Timer A ..................................................................................... 132 Section 11 Figure 11.1 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Figure 11.6 Figure 11.7 Figure 11.8 Timer V Block Diagram of Timer V ..................................................................................... 138 Increment Timing with Internal Clock .................................................................... 145 Increment Timing with External Clock................................................................... 145 OVF Set Timing ...................................................................................................... 145 CMFA and CMFB Set Timing................................................................................ 146 TMOV Output Timing ............................................................................................ 146 Clear Timing by Compare Match............................................................................ 146 Clear Timing by TMRIV Input ............................................................................... 147
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Figure 11.9 Pulse Output Example ............................................................................................. 148 Figure 11.10 Example of Pulse Output Synchronized to TRGV Input....................................... 149 Figure 11.11 Contention between TCNTV Write and Clear ...................................................... 150 Figure 11.12 Contention between TCORA Write and Compare Match ..................................... 151 Figure 11.13 Internal Clock Switching and TCNTV Operation ................................................. 151 Section 12 Timer W Figure 12.1 Timer W Block Diagram ......................................................................................... 155 Figure 12.2 Free-Running Counter Operation ............................................................................ 166 Figure 12.3 Periodic Counter Operation..................................................................................... 166 Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1)........................................................ 167 Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 167 Figure 12.6 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 167 Figure 12.7 Input Capture Operating Example........................................................................... 168 Figure 12.8 Buffer Operation Example (Input Capture)............................................................. 169 Figure 12.9 PWM Mode Example (1) ........................................................................................ 170 Figure 12.10 PWM Mode Example (2) ...................................................................................... 170 Figure 12.11 Buffer Operation Example (Output Compare) ...................................................... 171 Figure 12.12 PWM Mode Example (TOB, TOC, and TOD = 0: initial output values are set to 0) ............................... 172 Figure 12.13 PWM Mode Example (TOB, TOC, and TOD = 1: initial output values are set to 1) ............................... 173 Figure 12.14 Count Timing for Internal Clock Source ............................................................... 174 Figure 12.15 Count Timing for External Clock Source.............................................................. 174 Figure 12.16 Output Compare Output Timing ........................................................................... 175 Figure 12.17 Input Capture Input Signal Timing........................................................................ 175 Figure 12.18 Timing of Counter Clearing by Compare Match................................................... 176 Figure 12.19 Buffer Operation Timing (Compare Match).......................................................... 176 Figure 12.20 Buffer Operation Timing (Input Capture) ............................................................. 177 Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match .................................. 177 Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture...................................... 178 Figure 12.23 Timing of Status Flag Clearing by CPU................................................................ 178 Figure 12.24 Contention between TCNT Write and Clear ......................................................... 179 Figure 12.25 Internal Clock Switching and TCNT Operation.................................................... 180 Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW Occur at the Same Timing ..................................................................................... 181 Section 13 Watchdog Timer Figure 13.1 Block Diagram of Watchdog Timer ........................................................................ 183 Figure 13.2 Watchdog Timer Operation Example...................................................................... 187
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Section 14 Figure 14.1 Figure 14.2 Figure 14.3
Serial Communication Interface 3 (SCI3) Block Diagram of SCI3........................................................................................... 190 Data Format in Asynchronous Communication ...................................................... 205 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) ............. 205 Figure 14.4 Sample SCI3 Initialization Flowchart ..................................................................... 206 Figure 14.5 Example SCI3 Operation in Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) ........................................................................... 207 Figure 14.6 Sample Serial Transmission Flowchart (Asynchronous Mode) .............................. 208 Figure 14.7 Example SCI3 Operation in Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) ........................................................................... 209 Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous mode) (1)...................... 211 Figure 14.8 Sample Serial Reception Data Flowchart (2) .......................................................... 212 Figure 14.9 Data Format in Clocked Synchronous Communication .......................................... 213 Figure 14.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode...... 215 Figure 14.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode) ................ 216 Figure 14.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode............... 217 Figure 14.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)...................... 218 Figure 14.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations (Clocked Synchronous Mode) ........................................ 220 Figure 14.15 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) .......................................... 222 Figure 14.16 Sample Multiprocessor Serial Transmission Flowchart ........................................ 223 Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 225 Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 226 Figure 14.18 Example of SCI3 Operation in Reception Using Multiprocessor Format (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) .............................. 227 Figure 14.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 230 Section 15 I2C Bus Interface 2 (IIC2) Figure 15.1 Block Diagram of I2C Bus Interface 2..................................................................... 232 Figure 15.2 External Circuit Connections of I/O Pins ................................................................ 233 Figure 15.3 I2C Bus Formats ...................................................................................................... 246 Figure 15.4 I2C Bus Timing........................................................................................................ 246 Figure 15.5 Master Transmit Mode Operation Timing (1)......................................................... 248 Figure 15.6 Master Transmit Mode Operation Timing (2)......................................................... 248 Figure 15.7 Master Receive Mode Operation Timing (1) .......................................................... 250 Figure 15.8 Master Receive Mode Operation Timing (2) .......................................................... 251 Figure 15.9 Slave Transmit Mode Operation Timing (1) ........................................................... 252 Figure 15.10 Slave Transmit Mode Operation Timing (2) ......................................................... 253
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Figure 15.11 Figure 15.12 Figure 15.13 Figure 15.14 Figure 15.15 Figure 15.16 Figure 15.17 Figure 15.18 Figure 15.19 Figure 15.20 Figure 15.21 Section 16 Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4 Figure 16.5 Figure 16.6 Section 17 Figure 17.1 Figure 17.2 Figure 17.3 Figure 17.4 Figure 17.5 Figure 17.6 Figure 17.7 Section 18 Figure 18.1 Figure 18.2 Figure 18.3 Figure 18.4 Figure 18.5
Slave Receive Mode Operation Timing (1)........................................................... 254 Slave Receive Mode Operation Timing (2)........................................................... 254 Clocked Synchronous Serial Transfer Format....................................................... 255 Transmit Mode Operation Timing......................................................................... 256 Receive Mode Operation Timing .......................................................................... 257 Block Diagram of Noise Conceler......................................................................... 257 Sample Flowchart for Master Transmit Mode....................................................... 258 Sample Flowchart for Master Receive Mode ........................................................ 259 Sample Flowchart for Slave Transmit Mode......................................................... 260 Sample Flowchart for Slave Receive Mode .......................................................... 261 The Timing of the Bit Synchronous Circuit .......................................................... 263 A/D Converter Block Diagram of A/D Converter ........................................................................... 266 A/D Conversion Timing .......................................................................................... 272 External Trigger Input Timing ................................................................................ 273 A/D Conversion Accuracy Definitions (1) .............................................................. 275 A/D Conversion Accuracy Definitions (2) .............................................................. 275 Analog Input Circuit Example................................................................................. 276 EEPROM Block Diagram of EEPROM ................................................................................... 278 EEPROM Bus Format and Bus Timing .................................................................. 280 Byte Write Operation .............................................................................................. 283 Page Write Operation .............................................................................................. 284 Current Address Read Operation............................................................................. 285 Random Address Read Operation ........................................................................... 286 Sequential Read Operation (when current address read is used)............................. 287 Power-On Reset and Low-Voltage Detection Circuits (Optional) Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit.... 290 Operational Timing of Power-On Reset Circuit...................................................... 294 Operational Timing of LVDR Circuit ..................................................................... 295 Operational Timing of LVDI Circuit....................................................................... 296 Timing for Operation/Release of Low-Voltage Detection Circuit .......................... 297
Section 19 Power Supply Circuit Figure 19.1 Power Supply Connection when Internal Step-Down Circuit is Used .................... 299 Figure 19.2 Power Supply Connection when Internal Step-Down Circuit is Not Used ............. 300 Section 21 Electrical Characteristics Figure 21.1 System Clock Input Timing..................................................................................... 351 Figure 21.2 RES Low Width Timing.......................................................................................... 352
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Figure 21.3 Figure 21.4 Figure 21.5 Figure 21.6 Figure 21.7 Figure 21.8
Input Timing............................................................................................................ 352 I2C Bus Interface Input/Output Timing ................................................................... 352 SCK3 Input Clock Timing ...................................................................................... 353 SCI Input/Output Timing in Clocked Synchronous Mode ...................................... 353 EEPROM Bus Timing............................................................................................. 354 Output Load Circuit ................................................................................................ 354
Appendix B I/O Port Block Diagrams Figure B.1 Port 1 Block Diagram (P17) ..................................................................................... 385 Figure B.2 Port 1 Block Diagram (P16 to P14) .......................................................................... 386 Figure B.3 Port 1 Block Diagram (P12, P11) ............................................................................. 387 Figure B.4 Port 1 Block Diagram (P10) ..................................................................................... 388 Figure B.5 Port 2 Block Diagram (P22) ..................................................................................... 389 Figure B.6 Port 2 Block Diagram (P21) ..................................................................................... 390 Figure B.7 Port 2 Block Diagram (P20) ..................................................................................... 391 Figure B.8 Port 5 Block Diagram (P57, P56) ............................................................................. 392 Figure B.9 Port 5 Block Diagram (P55) ..................................................................................... 393 Figure B.10 Port 5 Block Diagram (P54 to P50) ........................................................................ 394 Figure B.11 Port 7 Block Diagram (P76) ................................................................................... 395 Figure B.12 Port 7 Block Diagram (P75) ................................................................................... 396 Figure B.13 Port 7 Block Diagram (P74) ................................................................................... 397 Figure B.14 Port 8 Block Diagram (P87 to P85) ........................................................................ 398 Figure B.15 Port 8 Block Diagram (P84 to P81) ........................................................................ 399 Figure B.16 Port 8 Block Diagram (P80) ................................................................................... 400 Figure B.17 Port B Block Diagram (PB7 to PB0) ...................................................................... 401 Appendix D Package Dimensions Figure D.1 FP-64E Package Dimensions ................................................................................... 405 Figure D.2 FP-64A Package Dimensions ................................................................................... 406 Figure D.3 FP-48F Package Dimensions.................................................................................... 407 Figure D.4 FP-48B Package Dimensions ................................................................................... 408 Figure D.5 TNP-48 Package Dimensions................................................................................... 409 Appendix E EEPROM Stacked-Structure Cross-Sectional View Figure E.1 EEPROM Stacked-Structure Cross-Sectional View ................................................. 410
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Tables
Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 9 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 24 Table 2.2 Data Transfer Instructions....................................................................................... 25 Table 2.3 Arithmetic Operations Instructions (1) ................................................................... 26 Table 2.3 Arithmetic Operations Instructions (2) ................................................................... 27 Table 2.4 Logic Operations Instructions................................................................................. 28 Table 2.5 Shift Instructions..................................................................................................... 28 Table 2.6 Bit Manipulation Instructions (1)............................................................................ 29 Table 2.6 Bit Manipulation Instructions (2)............................................................................ 30 Table 2.7 Branch Instructions ................................................................................................. 31 Table 2.8 System Control Instructions.................................................................................... 32 Table 2.9 Block Data Transfer Instructions ............................................................................ 33 Table 2.10 Addressing Modes .................................................................................................. 35 Table 2.11 Absolute Address Access Ranges ........................................................................... 36 Table 2.12 Effective Address Calculation (1)........................................................................... 38 Table 2.12 Effective Address Calculation (2)........................................................................... 39 Section 3 Exception Handling Table 3.1 Exception Sources and Vector Address .................................................................. 49 Table 3.2 Interrupt Wait States ............................................................................................... 60 Section 4 Address Break Table 4.1 Access and Data Bus Used ..................................................................................... 65 Section 5 Clock Pulse Generators Table 5.1 Crystal Resonator Parameters ................................................................................. 71 Section 6 Power-Down Modes Table 6.1 Operating Frequency and Waiting Time................................................................. 77 Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling ........ 81 Table 6.3 Internal State in Each Operating Mode................................................................... 82 Section 7 ROM Table 7.1 Setting Programming Modes .................................................................................. 93 Table 7.2 Boot Mode Operation ............................................................................................. 95 Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible ...................................................................................... 96 Table 7.4 Reprogram Data Computation Table .................................................................... 100
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Table 7.5 Table 7.6 Table 7.7
Additional-Program Data Computation Table ...................................................... 100 Programming Time ............................................................................................... 100 Flash Memory Operating States............................................................................ 105
Section 10 Timer A Table 10.1 Pin Configuration.................................................................................................. 132 Section 11 Timer V Table 11.1 Pin Configuration.................................................................................................. 138 Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions ............................... 141 Section 12 Timer W Table 12.1 Timer W Functions ............................................................................................... 154 Table 12.2 Pin Configuration.................................................................................................. 156 Section 14 Serial Communication Interface 3 (SCI3) Table 14.1 Pin Configuration.................................................................................................. 191 Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 199 Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 200 Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ...... 201 Table 14.3 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 202 Table 14.4 Examples of BBR Setting for Various Bit Rates (Clocked Synchronous Mode) (1)......................................................................... 203 Table 14.4 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2)......................................................................... 204 Table 14.5 SSR Status Flags and Receive Data Handling ...................................................... 210 Table 14.6 SCI3 Interrupt Requests........................................................................................ 228 Section 15 I2C Bus Interface 2 (IIC2) Table 15.1 I2C Bus Interface Pins........................................................................................... 233 Table 15.2 Transfer Rate ........................................................................................................ 235 Table 15.3 Interrupt Requests................................................................................................. 262 Table 15.4 Time for Monitoring SCL..................................................................................... 263 Section 16 A/D Converter Table 16.1 Pin Configuration.................................................................................................. 267 Table 16.2 Analog Input Channels and Corresponding ADDR Registers .............................. 268 Table 16.3 A/D Conversion Time (Single Mode)................................................................... 273 Section 17 EEPROM Table 17.1 Pin Configuration.................................................................................................. 279 Table 17.2 Slave Addresses .................................................................................................... 282
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Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) Table 18.1 LVDCR Settings and Select Functions................................................................. 292 Section 21 Electrical Characteristics Table 21.1 Absolute Maximum Ratings ................................................................................. 315 Table 21.2 DC Characteristics (1)........................................................................................... 318 Table 21.2 DC Characteristics (2)........................................................................................... 322 Table 21.2 DC Characteristics (3)........................................................................................... 323 Table 21.3 AC Characteristics ................................................................................................ 324 Table 21.4 I2C Bus Interface Timing ...................................................................................... 326 Table 21.5 Serial Communication Interface (SCI) Timing..................................................... 327 Table 21.6 A/D Converter Characteristics .............................................................................. 328 Table 21.7 Watchdog Timer Characteristics........................................................................... 329 Table 21.8 Flash Memory Characteristics .............................................................................. 330 Table 21.9 EEPROM Characteristics...................................................................................... 332 Table 21.10 Power-Supply-Voltage Detection Circuit Characteristics................................. 333 Table 21.11 Power-On Reset Circuit Characteristics............................................................ 334 Table 21.12 DC Characteristics (1)....................................................................................... 337 Table 21.12 DC Characteristics (2)....................................................................................... 341 Table 21.12 DC Characteristics (3)....................................................................................... 342 Table 21.13 AC Characteristics ............................................................................................ 343 Table 21.14 I2C Bus Interface Timing .................................................................................. 345 Table 21.15 Serial Communication Interface (SCI) Timing................................................. 346 Table 21.16 A/D Converter Characteristics .......................................................................... 347 Table 21.17 Watchdog Timer Characteristics....................................................................... 348 Table 21.18 EEPROM Characteristics.................................................................................. 349 Table 21.19 Power-Supply-Voltage Detection Circuit Characteristics................................. 350 Table 21.20 Power-On Reset Circuit Characteristics............................................................ 351 Appendix A Table A.1 Table A.2 Table A.2 Table A.2 Table A.3 Table A.4 Table A.5 Instruction Set Instruction Set ....................................................................................................... 357 Operation Code Map (1) ....................................................................................... 370 Operation Code Map (2) ....................................................................................... 371 Operation Code Map (3) ....................................................................................... 372 Number of Cycles in Each Instruction.................................................................. 374 Number of Cycles in Each Instruction.................................................................. 375 Combinations of Instructions and Addressing Modes .......................................... 384
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Section 1 Overview
Section 1 Overview
1.1 Features
* High-speed H8/300H central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 CPU on an object level Sixteen 16-bit general registers 62 basic instructions * Various peripheral functions Timer A (can be used as a time base for a clock) Timer V (8-bit timer) Timer W (16-bit timer) Watchdog timer SCI (Asynchronous or clocked synchronous serial communication interface) I2C Bus Interface (conforms to the I2C bus interface format that is advocated by Philips Electronics) 10-bit A/D converter
Rev.5.00 Nov. 02, 2005 Page 1 of 418 REJ09B0028-0500
Section 1 Overview
* On-chip memory
Model On-Chip Power-On Reset and LowVoltage Detecting Circuit Version ROM 32 kbytes 32 kbytes 24 kbytes 16 kbytes 12 kbytes 8 kbytes 32 kbytes
Product Classification Flash memory version TM (F-ZTAT version) Mask ROM version
Standard Version
RAM 2,048 bytes 1,024 bytes 1,024 bytes 512 bytes 512 bytes 512 bytes 2,048 bytes
Remarks
H8/3694F HD64F3694 HD64F3694G H8/3694 H8/3693 H8/3692 H8/3691 H8/3690 HD6433694 HD6433694G HD6433693 HD6433693G HD6433692 HD6433692G HD6433691 HD6433691G HD6433690 HD6433690G HD64N3694G
EEPROM stacked version (512 bytes)
Flash memory version Mask-ROM version
H8/3694N
HD6483694G
32 kbytes
1,024 bytes
* General I/O ports I/O pins: 29 I/O pins (27 I/O pins for H8/3694N), including 8 large current ports (IOL = 20 mA, @VOL = 1.5 V) Input-only pins: 8 input pins (also used for analog input) * EEPROM interface (only for H8/3694N) I2C bus interface (conforms to the I2C bus interface format that is advocated by Philips Electronics) * Supports various power-down modes Note: F-ZTATTM is a trademark of Renesas Technology Corp.
Rev.5.00 Nov. 02, 2005 Page 2 of 418 REJ09B0028-0500
Section 1 Overview
* Compact package
Package LQFP-64 QFP-64 LQFP-48 LQFP-48 QFN-48 Code FP-64E FP-64A FP-48F FP-48B TNP-48 Body Size 14.0 x 14.0 mm 7.0 x 7.0 mm 10.0 x 10.0 mm Pin Pitch 0.5 mm 0.8 mm 0.65 mm 0.5 mm 0.5 mm
10.0 x 10.0 mm 7.0 x 7.0 mm
Only LQFP-64 (FP-64E) for H8/3694N package
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Section 1 Overview
1.2
VCC VSS VCL
Internal Block Diagram
OSC1 OSC2 TEST RES NMI
X1 X2
P10/TMOW P11 P12 P14/IRQ0 P15/IRQ1 P16/IRQ2 P17/IRQ3/TRGV
Data bus (lower)
Port 1
Port 8
ROM RAM
Subclock generator
System clock generator
CPU H8/300H
P80/FTCI P81/FTIOA P82/FTIOB P83/FTIOC P84/FTIOD P85 P86 P87
P74/TMRIV P75/TMCIV P76/TMOV
Timer W
SCI3 P50/WKP0 P51/WKP1 P52/WKP2 P53/WKP3 P54/WKP4 P55/WKP5/ADTRG P56/SDA P57/SCL PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7
Timer A
Timer V
IIC2
A/D converter
POR/LVD (optional)
Data bus (upper) Address bus
Port B
Port 5
P20/SCK3 P21/RXD P22/TXD
Port 2
Watchdog timer
Port 7
AVCC
Figure 1.1 Internal Block Diagram of H8/3694 Group of F-ZTATTM and Mask-ROM Versions
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Section 1 Overview
OSC1 OSC2
TEST
RES
NMI
VCC
VSS
VCL
X1 X2
P10/TMOW P11 P12 P14/IRQ0 P15/IRQ1 P16/IRQ2 P17/IRQ3/TRGV
Data bus (lower)
Port 1
Port 8
ROM RAM
Subclock generator
System clock generator
CPU H8/300H
P80/FTCI P81/FTIOA P82/FTIOB P83/FTIOC P84/FTIOD P85 P86 P87
P74/TMRIV P75/TMCIV P76/TMOV
Timer W
SCI3 P50/WKP0 P51/WKP1 P52/WKP2 P53/WKP3 P54/WKP4 P55/WKP5/ADTRG P56/SDA P57/SCL PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7
Timer A
Timer V
SDA SCL
IIC2
I C bus
A/D converter
POR/LVD (optional)
Port B
2
Data bus (upper) Address bus
Port 5
P20/SCK3 P21/RXD P22/TXD
Port 2
Watchdog timer
Port 7
AVCC
EEPROM
Note: The HD64N3694G is a stacked-structure product in which an EEPROM chip is mounted on the HD64F3694G (F-ZTATTM version). The HD6483694G is a stacked-structure product in which an EEPROM chip is mounted on the HD6433694G (mask-ROM version).
Figure 1.2 Internal Block Diagram of H8/3694N (EEPROM Stacked Version)
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Section 1 Overview
1.3
Pin Arrangement
P84/FTIOD P83/FTIOC P82/FTIOB P81/FTIOA P20/SCK3 P80/FTCI P21/RXD P22/TXD
NMI
P87
P86
P85
NC
NC
NC
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
NC NC P14/IRQ0 P15/IRQ1 P16/IRQ2 P17/IRQ3/TRGV PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 NC NC
NC
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
H8/3694 Group Top view
NC NC P76/TMOV P75/TMCIV P74/TMRIV P57/SCL P56/SDA P12 P11 P10/TMOW P55/WKP5/ADTRG P54/WKP4 P53/WKP3 P52/WKP2 NC NC
NC
TEST
VSS
NC
NC
P50/WKP0
Note: Do not connect NC pins (these pins are not connected to the internal circuitry).
Figure 1.3 Pin Arrangement of H8/3694 Group of F-ZTATTM and Mask-ROM Versions (FP-64E, FP-64A)
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P51/WKP1
AVCC
RES
OSC2
OSC1
VCC
VCL
NC
X2
X1
Section 1 Overview
P84/FTIOD
P83/FTIOC
P82/FTIOB
P81/FTIOA
P20/SCK3
P80/FTCI
P21/RXD
P22/TXD
36 35 34 33 32 31 30 29 28 27 26 25 P14/IRQ0 P15/IRQ1 P16/IRQ2 P17/IRQ3/TRGV PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12
H8/3694 Group Top View
NMI
P87
P86
P85
24 23 22 21 20 19 18 17 16 15 14 13
P76/TMOV P75/TMCIV P74/TMRIV P57/SCL P56/SDA P12 P11 P10/TMOW P55/WKP5/ADTRG P54/WKP4 P53/WKP3 P52/WKP2
AVcc
X2
X1
RES
TEST
OSC2
OSC1
Vcc
P50/WKP0
Figure 1.4 Pin Arrangement of H8/3694 Group of F-ZTATTM and Mask-ROM Versions (FP-48F, FP-48B, TNP-48)
P51/WKP1
VCL
VSS
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Section 1 Overview
P84/FTIOD
P83/FTIOC
P82/FTIOB
P81/FTIOA
P20/SCK3
P80/FTCI
P21/RXD
P22/TXD
NMI
P87
P86
P85
NC
NC
NC
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NC NC P14/IRQ0 P15/IRQ1 P16/IRQ2 P17/IRQ3/TRGV PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 NC NC 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
H8/3694N Top View
NC
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
NC NC P76/TMOV P75/TMCIV P74/TMRIV SCL SDA P12 P11 P10/TMOW P55/WKP5/ADTRG P54/WKP4 P53/WKP3 P52/WKP2 NC NC
VSS
VCL
P50/WKP0
P51/WKP1
OSC2
OSC1
NC
AVcc
Note: Do not connect NC pins.
Figure 1.5 Pin Arrangement of H8/3694N (EEPROM Stacked Version) (FP-64E)
Rev.5.00 Nov. 02, 2005 Page 8 of 418 REJ09B0028-0500
TEST
RES
Vcc
NC
NC
NC
X2
X1
Section 1 Overview
1.4
Table 1.1
Pin Functions
Pin Functions
Pin No. FP-64E FP-64A 12 9 3 FP-48F FP-48B TNP-48 10 7 1
Type Power source pins
Symbol VCC VSS AVCC
I/O Input Input Input
Functions Power supply pin. Connect this pin to the system power supply. Ground pin. Connect this pin to the system power supply (0V). Analog power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply. Internal step-down power supply pin. Connect a capacitor of around 0.1 F between this pin and the Vss pin for stabilization. These pins connect with crystal or ceramic resonator for the system clock, or can be used to input an external clock. See section 5, Clock Pulse Generators, for a typical connection.
VCL
6
4
Input
Clock pins
OSC1 OSC2
11 10
9 8
Input Output
X1 X2 RES
5 4
3 2
Input Output
These pins connect with a 32.768 kHz crystal resonator for the subclock. See section 5, Clock Pulse Generators, for a typical connection. Reset pin. The pull-up resistor (typ. 150 k) is incorporated. When driven low, the chip is reset. Test pin. Connect this pin to Vss. Non-maskable interrupt request input pin. Be sure to pull-up by a pull-up resistor. External interrupt request input pins. Can select the rising or falling edge. External interrupt request input pins. Can select the rising or falling edge.
System control
7
5
Input
TEST Interrupt NMI pins IRQ0 to IRQ3
8 35 51 to 54
6 25
Input Input
37 to 40 Input 11 to 16 Input
WKP0 to 13, 14, WKP5 19 to 22
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Section 1 Overview
Pin No. FP-64E FP-64A 23 30 29 28 54 36 FP-48F FP-48B TNP-48 17 24 23 22 40 26
Type Timer A Timer V
Symbol TMOW TMOV TMCIV TMRIV TRGV
I/O Output Output Input Input Input Input I/O I/O
Functions This is an output pin for divided clocks. This is an output pin for waveforms generated by the output compare function. External event input pin. Counter reset input pin. Counter start trigger input pin. External event input pin. Output compare output/input capture input/ PWM output pin IIC data I/O pin. Can directly drive a bus by NMOS open-drain output.
Timer W
FTCI
FTIOA to 37 to 40 27 to 30 FTIOD I2C bus interface (IIC) SDA SCL 26*1 27*
1
20 21
I/O IIC clock I/O pin. Can directly drive a bus (EEPROM: by NMOS open-drain output. Input) Output Input I/O Input Input Input I/O Transmit data output pin Receive data input pin Clock I/O pin Analog input pin A/D converter trigger input pin. 8-bit input port. 7-bit I/O port.
Serial TXD communiRXD cation interface SCK3 (SCI) A/D AN7 to converter AN0 ADTRG I/O ports PB7 to PB0 P17 to P14, P12 to P10 P22 to P20 P57 to P50
46 45 44
36 35 34
55 to 62 41 to 48 22 16
55 to 62 41 to 48 51 to 54, 37 to 40 23 to 25 17 to 19
44 to 46 34 to 36
I/O
3-bit I/O port. 8-bit I/O port
20, 21, I/O 13, 14, 19 to 22, 13 to 16, 11, 12 26*2, 2 27*
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Section 1 Overview
Pin No. FP-64E FP-64A FP-48F FP-48B TNP-48
Type I/O ports
Symbol P76 to P74 P87 to P80
I/O I/O I/O
Functions 3-bit I/O port 8-bit I/O port.
28 to 30 22 to 24 36 to 43 26 to 33
Notes: 1. These pins are only available for the I2C bus interface in the H8/3694N. Since the I2C bus is disabled after canceling a reset, the ICE bit in ICCR1 must be set to 1 by using the program. 2. The P57 and P56 pins are not available in the H8/3694N.
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Section 1 Overview
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Section 2 CPU
Section 2 CPU
This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space. * Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs Additional eight 16-bit extended registers 32-bit transfer and arithmetic and logic instructions are added Signed multiply and divide instructions are added. * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers and eight 16-bit registers, or eight 32-bit registers * Sixty-two basic instructions 8/16/32-bit data transfer and arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 64-kbyte address space * High-speed operation All frequently-used instructions execute in one or two states 8/16/32-bit register-register add/subtract : 2 state 8 x 8-bit register-register multiply : 14 states 16 / 8-bit register-register divide : 14 states 16 x 16-bit register-register multiply : 22 states 32 / 16-bit register-register divide : 22 states * Power-down state Transition to power-down state by SLEEP instruction
CPU30H2D_000120030300
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Section 2 CPU
2.1
Address Space and Memory Map
The address space of this LSI is 64 kbytes, which includes the program area and the data area. Figures 2.1 show the memory map.
HD64F3694, HD64F3694G (Flash memory version) H'0000 H'0033 H'0034 Interrupt vector HD6433690, HD6433690G (Mask ROM version) H'0000 H'0033 H'0034 Interrupt vector On-chip ROM (8 kbytes) H'1FFF H'2FFF H'0000 H'0033 H'0034 HD6433691, HD6433691G (Mask ROM version) Interrupt vector
On-chip ROM (12 kbytes)
On-chip ROM (32 kbytes)
Not used Not used
H'7FFF
Not used H'F730 Internal I/O register H'F74F Not used H'F780 (1-kbyte work area for flash memory programming) H'F74F H'F730 Internal I/O register H'F74F H'F730 Internal I/O register
Not used
Not used
H'FB7F H'FB80
On-chip RAM (2 kbytes)
(1-kbyte user area)
H'FD80 On-chip RAM (512 bytes)
H'FD80 On-chip RAM (512 bytes) H'FF7F H'FF80 Internal I/O register Internal I/O register H'FFFF
H'FF7F H'FF80 Internal I/O register H'FFFF
H'FF7F H'FF80 H'FFFF
Figure 2.1 Memory Map (1)
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Section 2 CPU
HD6433692, HD6433692G (Mask ROM version)
HD6433693, HD6433693G (Mask ROM version)
H'0000 H'0033 H'0034 Interrupt vector
H'0000 H'0033 H'0034
HD6433694, HD6433694G (Mask ROM version)
Interrupt vector
H'0000 H'0033 H'0034
Interrupt vector
On-chip ROM (16 kbytes)
On-chip ROM (24 kbytes)
H'3FFF
On-chip ROM (32 kbytes)
H'5FFF
Not used
H'7FFF
Not used
Not used
H'F730
Internal I/O register
H'F730
Internal I/O register
H'F730
Internal I/O register
H'F74F
H'F74F
Not used
Not used
H'F74F
Not used H'FB80
H'FB80 On-chip RAM (1 kbyte)
H'FD80
On-chip RAM (1 kbyte)
On-chip RAM (512 bytes) H'FF7F H'FF80 Internal I/O register
H'FFFF
H'FFFF
H'FF7F H'FF80 Internal I/O register
H'FF7F H'FF80 Internal I/O register
H'FFFF
Figure 2.1 Memory Map (2)
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Section 2 CPU
HD64N3694G HD6483694G (On-chip EEPROM module) H'0000 User area (512 bytes)
H'01FF
Not used
H'FF09 Slave address register
Not used
Figure 2.1 Memory Map (3)
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Section 2 CPU
2.2
Register Configuration
The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition code register (CCR).
General Registers (ERn)
15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 E0 E1 E2 E3 E4 E5 E6 E7 (SP) 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0
Control Registers (CR)
23 PC 0
76543210
CCR I UI H U N Z V C
[Legend]
SP: PC: CCR: I: UI: Stack pointer Program counter Condition-code register Interrupt mask bit User bit H: U: N: Z: V: C: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag
Figure 2.2 CPU Registers
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Section 2 CPU
2.2.1
General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-bit registers. The usage of each register can be selected independently.
* Address registers * 32-bit registers * 16-bit registers * 8-bit registers
E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) RH registers (R0H to R7H)
Figure 2.3 Usage of General Registers
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Section 2 CPU
General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the relationship between stack pointer and the stack area.
Free area SP (ER7)
Stack area
Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0). The PC is initialized when the start address is loaded by the vector address generated during reset exception-handling sequence. 2.2.3 Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1 by reset exception-handling sequence, but other bits are not initialized. Some instructions leave flag bits unchanged. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. For the action of each instruction on the flag bits, see appendix A.1, Instruction List.
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Section 2 CPU
Bit 7
Bit Name I
Initial Value 1
R/W R/W
Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence.
6
UI
Undefined R/W
User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions.
5
H
Undefined R/W
Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise.
4
U
Undefined R/W
User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions.
3
N
Undefined R/W
Negative Flag Stores the value of the most significant bit of data as a sign bit.
2
Z
Undefined R/W
Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
1
V
Undefined R/W
Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times.
0
C
Undefined R/W
Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit manipulation instructions.
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Section 2 CPU
2.3
Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.3.1 General Register Data Formats
Figure 2.5 shows the data formats in general registers.
Data Type
1-bit data
General Register
RnH
Data Format
7 0 Don't care
7
0
76 54 32 10
1-bit data
RnL
Don't care
76 54 32 10
7
4-bit BCD data RnH Upper
43
Lower
0
Don't care
7
4-bit BCD data RnL
43
Upper Lower
0
Don't care
7
Byte data RnH
0
Don't care
MSB
LSB
7
Byte data RnL
0 LSB
Don't care
MSB
Figure 2.5 General Register Data Formats (1)
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Section 2 CPU
Data Type Word data
General Register Rn
Data Format
15
0
Word data
En
15 0
MSB
LSB
MSB
LSB
16 15
0
Longword data
ERn
31
MSB
LSB
[Legend]
ERn: En: Rn: RnH: RnL: MSB: LSB: General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit
Figure 2.5 General Register Data Formats (2)
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Section 2 CPU
2.3.2
Memory Data Formats
Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches. When ER7 (SP) is used as an address register to access the stack area, the operand size should be word or longword.
Data Type Address
7 1-bit data Address L 7 6 5 4 3 2 1
Data Format
0 0
Byte data
Address L
MSB
LSB
Word data
Address 2M Address 2M+1
MSB LSB
Longword data
Address 2N Address 2N+1 Address 2N+2 Address 2N+3
MSB
LSB
Figure 2.6 Memory Data Formats
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Section 2 CPU
2.4
2.4.1
Instruction Set
Table of Instructions Classified by Function
The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below. Table 2.1
Symbol Rd Rs Rn ERn (EAd) (EAs) CCR N Z V C PC SP #IMM disp + - x / :3/:8/:16/:24 Note: *
Operation Notation
Description General register (destination)* General register (source)* General register* General register (32-bit register or address register) Destination operand Source operand Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical XOR Move NOT (logical complement) 3-, 8-, 16-, or 24-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7).
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Section 2 CPU
Table 2.2
Instruction MOV
Data Transfer Instructions
Size* B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) Rd, Cannot be used in this LSI. Rs (EAs) Cannot be used in this LSI. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP.
MOVFPE MOVTPE POP
B B W/L
PUSH
W/L
Note:
*
Refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.3
Instruction ADD SUB
Arithmetic Operations Instructions (1)
Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder.
ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU
B
B/W/L
L B
B/W
MULXS
B/W
DIVXU
B/W
Note:
*
Refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.3
Instruction DIVXS
Arithmetic Operations Instructions (2)
Size* B/W Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit.
CMP
B/W/L
NEG
B/W/L
EXTU
W/L
EXTS
W/L
Note:
*
Refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.4
Instruction AND
Logic Operations Instructions
Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. (Rd) (Rd) Takes the one's complement (logical complement) of general register contents.
OR
B/W/L
XOR
B/W/L
NOT
B/W/L
Note:
*
Refers to the operand size. B: Byte W: Word L: Longword
Table 2.5
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: *
Shift Instructions
Size* B/W/L B/W/L B/W/L B/W/L Function Rd (shift) Rd Performs an arithmetic shift on general register contents. Rd (shift) Rd Performs a logical shift on general register contents. Rd (rotate) Rd Rotates general register contents. Rd (rotate) Rd Rotates general register contents through the carry flag.
Refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.6
Instruction BSET
Bit Manipulation Instructions (1)
Size* B Function 1 ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. 0 ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ( of ) ( of ) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ( of ) Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. C ( of ) C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ( of ) C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ( of ) C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ( of ) C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
BCLR
B
BNOT
B
BTST
B
BAND
B
BIAND
B
BOR
B
BIOR
B
Note:
*
Refers to the operand size. B: Byte
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Section 2 CPU
Table 2.6
Instruction BXOR
Bit Manipulation Instructions (2)
Size* B Function C ( of ) C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ( of ) C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. ( of ) C Transfers a specified bit in a general register or memory operand to the carry flag. ( of ) C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. C ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand. C ( of ) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data.
BIXOR
B
BLD
B
BILD
B
BST
B
BIST
B
Note:
*
Refers to the operand size. B: Byte
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Section 2 CPU
Table 2.7
Instruction Bcc*
Branch Instructions
Size -- Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z(N V) = 0 Z(N V) = 1
JMP BSR JSR RTS Note : *
-- -- -- --
Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine
Bcc is the general name for conditional branch instructions.
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Section 2 CPU
Table 2.8
Instruction TRAPA RTE SLEEP LDC
System Control Instructions
Size* -- -- -- B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access. CCR (EAd) Transfers the CCR contents to a destination location. The condition code register size is one byte, but in transfer to memory, data is written by word access. CCR #IMM CCR Logically ANDs the CCR with immediate data. CCR #IMM CCR Logically ORs the CCR with immediate data. CCR #IMM CCR Logically XORs the CCR with immediate data. PC + 2 PC Only increments the program counter.
STC
B/W
ANDC ORC XORC NOP Note: *
B B B --
Refers to the operand size. B: Byte W: Word
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Section 2 CPU
Table 2.9
Instruction EEPMOV.B
Block Data Transfer Instructions
Size -- Function if R4L 0 then Repeat @ER5+ @ER6+, R4L-1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5+ @ER6+, R4-1 R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed.
EEPMOV.W
--
2.4.2
Basic Instruction Formats
H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.7 shows examples of instruction formats. * Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register Field Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. * Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00). * Condition Field Specifies the branching condition of Bcc instructions.
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(1) Operation field only op NOP, RTS, etc.
(2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension op EA(disp) rn rm MOV.B @(d:16, Rn), Rm
(4) Operation field, effective address extension, and condition field op cc EA(disp) BRA d:8
Figure 2.7 Instruction Formats
2.5
Addressing Modes and Effective Address Calculation
The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses a subset of these addressing modes. Addressing modes that can be used differ depending on the instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing Modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or the absolute addressing mode (@aa:8) to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
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Table 2.10 Addressing Modes
No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:24,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
Register Direct--Rn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. Register Indirect--@ERn The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory. Register Indirect with Displacement--@(d:16, ERn) or @(d:24, ERn) A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand. A 16-bit displacement is sign-extended when added. Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn * Register indirect with post-increment--@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. For the word or longword access, the register value should be even.
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* Register indirect with pre-decrement--@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the lower 24 bits of the result is the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For the word or longword access, the register value should be even. Absolute Address--@aa:8, @aa:16, @aa:24 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24) For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the entire address space. The access ranges of absolute addresses for the group of this LSI are those shown in table 2.11, because the upper 8 bits are ignored. Table 2.11 Absolute Address Access Ranges
Absolute Address 8 bits (@aa:8) 16 bits (@aa:16) 24 bits (@aa:24) Access Range H'FF00 to H'FFFF H'0000 to H'FFFF H'0000 to H'FFFF
Immediate--#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. Program-Counter Relative--@(d:8, PC) or @(d:16, PC) This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction,
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so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. Memory Indirect--@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The memory operand is accessed by longword access. The first byte of the memory operand is ignored, generating a 24-bit branch address. Figure 2.8 shows how to specify branch address for in memory indirect mode. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF). Note that the first part of the address range is also the exception vector area.
Specified by @aa:8
Dummy Branch address
Figure 2.8 Branch Address Specification in Memory Indirect Mode
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Section 2 CPU
2.5.2
Effective Address Calculation
Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. Table 2.12 Effective Address Calculation (1)
No
1
Addressing Mode and Instruction Format
Register direct(Rn)
Effective Address Calculation
Effective Address (EA)
Operand is general register contents.
op
rm
rn
31
General register contents
2
Register indirect(@ERn)
0
23
0
op
r
3
Register indirect with displacement @(d:16,ERn) or @(d:24,ERn)
31
General register contents
0
23 0
op
r
disp
31
Sign extension
0
disp
4
Register indirect with post-increment or pre-decrement *Register indirect with post-increment @ERn+
31
General register contents
0
23
0
op
r
1, 2, or 4
*Register indirect with pre-decrement @-ERn
31
General register contents
0 23
0
op
r
1, 2, or 4
The value to be added or subtracted is 1 when the operand is byte size, 2 for word size, and 4 for longword size.
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Table 2.12 Effective Address Calculation (2)
No 5
Addressing Mode and Instruction Format
Absolute address
Effective Address Calculation
Effective Address (EA)
@aa:8 op abs
23 H'FFFF
87
0
@aa:16 op abs
23
16 15
0
Sign extension
@aa:24 op abs 23 0
6
Immediate
#xx:8/#xx:16/#xx:32 op IMM
Operand is immediate data.
7
Program-counter relative @(d:8,PC) @(d:16,PC)
23
PC contents
0
op
disp
23
Sign extension
0 disp 23 0
8
Memory indirect @@aa:8
23 op abs H'0000 15
87 abs
0
0
Memory contents
23
16 15 H'00
0
[Legend] r, rm, rn: op: disp: IMM: abs:
Register field Operation field Displacement Immediate data Absolute address
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Section 2 CPU
2.6
Basic Bus Cycle
CPU operation is synchronized by a system clock () or a subclock (SUB). The period from a rising edge of or SUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
Bus cycle
T1 state
or SUB
T2 state
Internal address bus
Address
Internal read signal Internal data bus (read access)
Read data
Internal write signal
Internal data bus (write access)
Write data
Figure 2.9 On-Chip Memory Access Cycle
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2.6.2
On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing states of each register, refer to section 20.1, Register Addresses (Address Order). Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data bus width can be accessed by byte or word size. When a register with 8-bit data bus width is accessed by word size, a bus cycle occurs twice. In two-state access, the operation timing is the same as that for on-chip memory. Figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral module.
Bus cycle
T1 state
or SUB
T2 state
T3 state
Internal address bus Internal read signal Internal data bus (read access) Internal write signal
Internal data bus (write access)
Address
Read data
Write data
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
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Section 2 CPU
2.7
CPU States
There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode and subactive mode. For the program halt state there are a sleep mode, standby mode, and sub-sleep mode. These states are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and program halt state, refer to section 6, Power-Down Modes. For details on exception processing, refer to section 3, Exception Handling.
CPU state
Reset state The CPU is initialized Program execution state
Active (high speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock Subactive mode The CPU executes successive program instructions at reduced speed, synchronized by the subclock
Power-down modes
Program halt state A state in which some or all of the chip functions are stopped to conserve power
Sleep mode
Standby mode
Subsleep mode Exceptionhandling state A transient state in which the CPU changes the processing flow due to a reset or an interrupt
Figure 2.11 CPU Operation States
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Reset cleared Reset state
Reset occurs
Exception-handling state
Reset occurs
Reset occurs
Interrupt source
Interrupt source
Exceptionhandling complete
Program halt state SLEEP instruction executed
Program execution state
Figure 2.12 State Transitions
2.8
2.8.1
Usage Notes
Notes on Data Access to Empty Areas
The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user. When data is transferred from CPU to empty areas, the transferred data will be lost. This action may also cause the CPU to malfunction. When data is transferred from an empty area to CPU, the contents of the data cannot be guaranteed. 2.8.2 EEPMOV Instruction
EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L, which starts from the address indicated by R5, to the address indicated by R6. Set R4L and R6 so that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the value of R6 must not change from H'FFFF to H'0000 during execution). 2.8.3 Bit Manipulation Instruction
The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units. Special care is required when using these instructions in cases where two registers are assigned to the same address or when a bit is directly manipulated for a port or a register containing a write-only bit, because this may rewrite data of a bit other than the bit to be manipulated.
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Bit manipulation for two registers assigned to the same address Example 1: Bit manipulation for the timer load register and timer counter (Applicable for timer B and timer C, not for the group of this LSI.) Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address. When a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations takes place. 1. Data is read in byte units. 2. The CPU sets or resets the bit to be manipulated with the bit manipulation instruction. 3. The written data is written again in byte units to the timer load register. The timer is counting, so the value read is not necessarily the same as the value in the timer load register. As a result, bits other than the intended bit in the timer counter may be modified and the modified value may be written to the timer load register.
Read Count clock Timer counter
Reload
Write Timer load register
Internal data bus
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same Address Example 2: The BSET instruction is executed for port 5. P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level signal at P50 with a BSET instruction is shown below.
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* Prior to executing BSET instruction
P57 Input/output Pin state PCR5 PDR5 Input Low level 0 1 P56 Input High level 0 0 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Output Low level 1 0
* BSET instruction executed instruction BSET #0, @PDR5 The BSET instruction is executed for port 5.
* After executing BSET instruction
P57 Input/output Pin state PCR5 PDR5 Input Low level 0 0 P56 Input High level 0 1 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Output High level 1 1
* Description on operation 1. When the BSET instruction is executed, first the CPU reads port 5. Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level input). P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a value of H'80, but the value read by the CPU is H'40. 2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41. 3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET instruction. As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR5.
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* Prior to executing BSET instruction MOV.B MOV.B MOV.B #80, R0L, R0L,
P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 1
R0L @RAM0 @PDR5
P56 Input High level 0 0 0
The PDR5 value (H'80) is written to a work area in memory (RAM0) as well as to PDR5.
P55 Output Low level 1 0 0
P54 Output Low level 1 0 0
P53 Output Low level 1 0 0
P52 Output Low level 1 0 0
P51 Output Low level 1 0 0
P50 Output Low level 1 0 0
* BSET instruction executed BSET #0, @RAM0 The BSET instruction is executed designating the PDR5 work area (RAM0).
* After executing BSET instruction MOV.B MOV.B @RAM0, R0L R0L, @PDR5
P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 1 P56 Input High level 0 0 0
The work area (RAM0) value is written to PDR5.
P55 Output Low level 1 0 0
P54 Output Low level 1 0 0
P53 Output Low level 1 0 0
P52 Output Low level 1 0 0
P51 Output Low level 1 0 0
P50 Output High level 1 1 1
Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as
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an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be input to this input pin. * Prior to executing BCLR instruction
P57 Input/output Pin state PCR5 PDR5 Input Low level 0 1 P56 Input High level 0 0 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Output Low level 1 0
* BCLR instruction executed BCLR #0, @PCR5 The BCLR instruction is executed for PCR5.
* After executing BCLR instruction
P57 Input/output Pin state PCR5 PDR5 Output Low level 1 1 P56 Output High level 1 0 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Input High level 0 0
* Description on operation 1. When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only register, the CPU reads a value of H'FF, even though the PCR5 value is actually H'3F. 2. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. 3. Finally, H'FE is written to PCR5 and BCLR instruction execution ends. As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However, bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins. To prevent this problem, store a copy of the PDR5 data in a work area in memory and manipulate data of the bit in the work area, then write this data to PDR5.
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* Prior to executing BCLR instruction MOV.B MOV.B MOV.B #3F, R0L, R0L,
P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 0
R0L @RAM0 @PCR5
P56 Input High level 0 0 0
The PCR5 value (H'3F) is written to a work area in memory (RAM0) as well as to PCR5.
P55 Output Low level 1 0 1
P54 Output Low level 1 0 1
P53 Output Low level 1 0 1
P52 Output Low level 1 0 1
P51 Output Low level 1 0 1
P50 Output Low level 1 0 1
* BCLR instruction executed BCLR #0, @RAM0 The BCLR instructions executed for the PCR5 work area (RAM0).
* After executing BCLR instruction MOV.B MOV.B @RAM0, R0L R0L, @PCR5
P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 0 P56 Input High level 0 0 0
The work area (RAM0) value is written to PCR5.
P55 Output Low level 1 0 1
P54 Output Low level 1 0 1
P53 Output Low level 1 0 1
P52 Output Low level 1 0 1
P51 Output Low level 1 0 1
P50 Output High level 0 0 0
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Section 3 Exception Handling
Section 3 Exception Handling
Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. * Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling starts. Exception handling is the same as exception handling by the RES pin. * Trap Instruction Exception handling starts when a trap instruction (TRAPA) is executed. The TRAPA instruction generates a vector address corresponding to a vector number from 0 to 3, as specified in the instruction code. Exception handling can be executed at all times in the program execution state, regardless of the setting of the I bit in CCR. * Interrupts External interrupts other than NMI and internal interrupts other than address break are masked by the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when the current instruction or exception handling ends, if an interrupt request has been issued.
3.1
Exception Sources and Vector Address
Table 3.1 shows the vector addresses and priority of each exception handling. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority. Table 3.1 Exception Sources and Vector Address
Exception Sources Reset Reserved for system use NMI Trap instruction (#0) (#1) (#2) (#3) Address break Break conditions satisfied Vector Number 0 1 to 6 7 8 9 10 11 12 Vector Address H'0000 to H'0001 H'0002 to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 Low Priority High
Relative Module RES pin Watchdog timer External interrupt pin CPU
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Section 3 Exception Handling
Relative Module CPU External interrupt pin
Exception Sources Direct transition by executing the SLEEP instruction IRQ0 Low-voltage detection interrupt* IRQ1 IRQ2 IRQ3 WKP
Vector Number 13 14
Vector Address H'001A to H'001B H'001C to H'001D
Priority High
15 16 17 18 19 20 21
H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B
Timer A Timer W
Overflow Reserved for system use Timer W input capture A /compare match A Timer W input capture B /compare match B Timer W input capture C /compare match C Timer W input capture D /compare match D Timer W overflow Timer V compare match A Timer V compare match B Timer V overflow SCI3 receive data full SCI3 transmit data empty SCI3 transmit end SCI3 receive error Transmit data empty Transmit end Receive data full Arbitration lost/Overrun error NACK detection Stop conditions detected A/D conversion end
Timer V
22
H'002C to H'002D
SCI3
23
H'002E to H'002F
IIC2
24
H'0030 to H'0031
A/D converter Note *
25
H'0032 to H'0033
Low
A low-voltage detection interrupt is enabled only in the product with an on-chip poweron reset and low-voltage detection circuit.
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Section 3 Exception Handling
3.2
Register Descriptions
Interrupts are controlled by the following registers. * * * * * Interrupt edge select register 1 (IEGR1) Interrupt edge select register 2 (IEGR2) Interrupt enable register 1 (IENR1) Interrupt flag register 1 (IRR1) Wakeup interrupt flag register (IWPR) Interrupt Edge Select Register 1 (IEGR1)
3.2.1
IEGR1 selects the direction of an edge that generates interrupt requests of pins NMI and IRQ3 to IRQ0.
Bit 7 Bit Name NMIEG Initial Value 0 R/W R/W Description NMI Edge Select 0: Falling edge of NMI pin input is detected 1: Rising edge of NMI pin input is detected 6 to 4 3 IEG3 All 1 0 R/W Reserved These bits are always read as 1. IRQ3 Edge Select 0: Falling edge of IRQ3 pin input is detected 1: Rising edge of IRQ3 pin input is detected 2 IEG2 0 R/W IRQ2 Edge Select 0: Falling edge of IRQ2 pin input is detected 1: Rising edge of IRQ2 pin input is detected 1 IEG1 0 R/W IRQ1 Edge Select 0: Falling edge of IRQ1 pin input is detected 1: Rising edge of IRQ1 pin input is detected 0 IEG0 0 R/W IRQ0 Edge Select 0: Falling edge of IRQ0 pin input is detected 1: Rising edge of IRQ0 pin input is detected
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Section 3 Exception Handling
3.2.2
Interrupt Edge Select Register 2 (IEGR2)
IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and WKP5 to WKP0.
Bit 7, 6 5 Bit Name WPEG5 Initial Value All 1 0 R/W R/W Description Reserved These bits are always read as 1. WKP5 Edge Select 0: Falling edge of WKP5(ADTRG) pin input is detected 1: Rising edge of WKP5(ADTRG) pin input is detected 4 WPEG4 0 R/W WKP4 Edge Select 0: Falling edge of WKP4 pin input is detected 1: Rising edge of WKP4 pin input is detected 3 WPEG3 0 R/W WKP3 Edge Select 0: Falling edge of WKP3 pin input is detected 1: Rising edge of WKP3 pin input is detected 2 WPEG2 0 R/W WKP2 Edge Select 0: Falling edge of WKP2 pin input is detected 1: Rising edge of WKP2 pin input is detected 1 WPEG1 0 R/W WKP1Edge Select 0: Falling edge of WKP1 pin input is detected 1: Rising edge of WKP1 pin input is detected 0 WPEG0 0 R/W WKP0 Edge Select 0: Falling edge of WKP0 pin input is detected 1: Rising edge of WKP0 pin input is detected
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Section 3 Exception Handling
3.2.3
Interrupt Enable Register 1 (IENR1)
IENR1 enables direct transition interrupts, timer A overflow interrupts, and external pin interrupts.
Bit 7 Bit Name IENDT Initial Value 0 R/W R/W Description Direct Transfer Interrupt Enable When this bit is set to 1, direct transition interrupt requests are enabled. 6 IENTA 0 R/W Timer A Interrupt Enable When this bit is set to 1, timer A overflow interrupt requests are enabled. 5 IENWP 0 R/W Wakeup Interrupt Enable This bit is an enable bit, which is common to the pins WKP5 to WKP0. When the bit is set to 1, interrupt requests are enabled. 4 3 IEN3 1 0 R/W Reserved This bit is always read as 1. IRQ3 Interrupt Enable When this bit is set to 1, interrupt requests of the IRQ3 pin are enabled. 2 IEN2 0 R/W IRQ2 Interrupt Enable When this bit is set to 1, interrupt requests of the IRQ2 pin are enabled. 1 IEN1 0 R/W IRQ1 Interrupt Enable When this bit is set to 1, interrupt requests of the IRQ1 pin are enabled. 0 IEN0 0 R/W IRQ0 Interrupt Enable When this bit is set to 1, interrupt requests of the IRQ0 pin are enabled.
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear operations are performed while I = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception handling for the interrupt will be executed after the clear instruction has been executed.
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Section 3 Exception Handling
3.2.4
Interrupt Flag Register 1 (IRR1)
IRR1 is a status flag register for direct transition interrupts, timer A overflow interrupts, and IRQ3 to IRQ0 interrupt requests.
Bit 7 Bit Name IRRDT Initial Value 0 R/W R/W Description Direct Transfer Interrupt Request Flag [Setting condition] When a direct transfer is made by executing a SLEEP instruction while DTON in SYSCR2 is set to 1. [Clearing condition] When IRRDT is cleared by writing 0 6 IRRTA 0 R/W Timer A Interrupt Request Flag [Setting condition] When the timer A counter value overflows [Clearing condition] When IRRTA is cleared by writing 0 5, 4 3 IRRI3 All 1 0 R/W Reserved These bits are always read as 1. IRQ3 Interrupt Request Flag [Setting condition] When IRQ3 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IRRI3 is cleared by writing 0 2 IRRI2 0 R/W IRQ2 Interrupt Request Flag [Setting condition] When IRQ2 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IRRI2 is cleared by writing 0 1 IRRI1 0 R/W IRQ1 Interrupt Request Flag [Setting condition] When IRQ1 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IRRI1 is cleared by writing 0
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Section 3 Exception Handling
Bit 0
Bit Name IRRl0
Initial Value 0
R/W R/W
Description IRQ0 Interrupt Request Flag [Setting condition] When IRQ0 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IRRI0 is cleared by writing 0
3.2.5
Wakeup Interrupt Flag Register (IWPR)
Initial Value All 1 0
IWPR is a status flag register for WKP5 to WKP0 interrupt requests.
Bit 7, 6 5 Bit Name IWPF5 R/W R/W Description Reserved These bits are always read as 1. WKP5 Interrupt Request Flag [Setting condition] When WKP5 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF5 is cleared by writing 0. 4 IWPF4 0 R/W WKP4 Interrupt Request Flag [Setting condition] When WKP4 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF4 is cleared by writing 0. 3 IWPF3 0 R/W WKP3 Interrupt Request Flag [Setting condition] When WKP3 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF3 is cleared by writing 0.
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Section 3 Exception Handling
Bit 2
Bit Name IWPF2
Initial Value 0
R/W R/W
Description WKP2 Interrupt Request Flag [Setting condition] When WKP2 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF2 is cleared by writing 0.
1
IWPF1
0
R/W
WKP1 Interrupt Request Flag [Setting condition] When WKP1 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF1 is cleared by writing 0.
0
IWPF0
0
R/W
WKP0 Interrupt Request Flag [Setting condition] When WKP0 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF0 is cleared by writing 0.
3.3
Reset Exception Handling
When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure that this LSI is reset at power-up, hold the RES pin low until the clock pulse generator output stabilizes. To reset the chip during operation, hold the RES pin low for at least 10 system clock cycles. When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling. The reset exception handling sequence is shown in figure 3.1. The reset exception handling sequence is as follows. However, for the reset exception handling sequence of the product with on-chip power-on reset circuit, refer to section 18, Power-On Reset and Low-Voltage Detection Circuits (Optional). 1. Set the I bit in the condition code register (CCR) to 1. 2. The CPU generates a reset exception handling vector address (from H'0000 to H'0001), the data in that address is sent to the program counter (PC) as the start address, and program execution starts from that address.
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Section 3 Exception Handling
3.4
3.4.1
Interrupt Exception Handling
External Interrupts
As the external interrupts, there are NMI, IRQ3 to IRQ0, and WKP5 to WKP0 interrupts. NMI Interrupt NMI interrupt is requested by input signal edge to pin NMI. This interrupt is detected by either rising edge sensing or falling edge sensing, depending on the setting of bit NMIEG in IEGR1. NMI is the highest-priority interrupt, and can always be accepted without depending on the I bit value in CCR. IRQ3 to IRQ0 Interrupts IRQ3 to IRQ0 interrupts are requested by input signals to pins IRQ3 to IRQ0. These four interrupts are given different vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG3 to IEG0 in IEGR1. When pins IRQ3 to IRQ0 are designated for interrupt input in PMR1 and the designated signal edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt. These interrupts can be masked by setting bits IEN3 to IEN0 in IENR1. WKP5 to WKP0 Interrupts WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0. These six interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits WPEG5 to WPEG0 in IEGR2. When pins WKP5 to WKP0 are designated for interrupt input in PMR5 and the designated signal edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an interrupt. These interrupts can be masked by setting bit IENWP in IENR1.
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Section 3 Exception Handling
Reset cleared
Initial program instruction prefetch Vector fetch Internal processing
RES
Internal address bus Internal read signal Internal write signal Internal data bus (16 bits)
(1)
(2)
(2)
(3)
(1) Reset exception handling vector address (H'0000) (2) Program start address (3) Initial program instruction
Figure 3.1 Reset Sequence 3.4.2 Internal Interrupts
Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the interrupt. For timer A interrupt requests and direct transfer interrupt requests generated by execution of a SLEEP instruction, this function is included in IRR1 and IENR1. When an on-chip peripheral module requests an interrupt, the corresponding interrupt request status flag is set to 1, requesting the CPU of an interrupt. These interrupts can be masked by writing 0 to clear the corresponding enable bit. 3.4.3 Interrupt Handling Sequence
Interrupts are controlled by an interrupt controller. Interrupt operation is described as follows. 1. If an interrupt occurs while the NMI or interrupt enable bit is set to 1, an interrupt request signal is sent to the interrupt controller.
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Section 3 Exception Handling
2. When multiple interrupt requests are generated, the interrupt controller requests to the CPU for the interrupt handling with the highest priority at that time according to table 3.1. Other interrupt requests are held pending. 3. The CPU accepts the NMI and address break without depending on the I bit value. Other interrupt requests are accepted, if the I bit is cleared to 0 in CCR; if the I bit is set to 1, the interrupt request is held pending. 4. If the CPU accepts the interrupt after processing of the current instruction is completed, interrupt exception handling will begin. First, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.2. The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. 5. Then, the I bit of CCR is set to 1, masking further interrupts excluding the NMI and address break. Upon return from interrupt handling, the values of I bit and other bits in CCR will be restored and returned to the values prior to the start of interrupt exception handling. 6. Next, the CPU generates the vector address corresponding to the accepted interrupt, and transfers the address to PC as a start address of the interrupt handling-routine. Then a program starts executing from the address indicated in PC. Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and the stack area is in the on-chip RAM.
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Section 3 Exception Handling
SP - 4
SP (R7)
CCR CCR*3 PCH PCL Even address
SP - 3 SP - 2 SP - 1 SP (R7)
Stack area
SP + 1
SP + 2 SP + 3 SP + 4
Prior to start of interrupt exception handling
PC and CCR saved to stack
After completion of interrupt exception handling
[Legend] PCH : Upper 8 bits of program counter (PC) PCL : Lower 8 bits of program counter (PC) CCR: Condition code register SP: Stack pointer Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt handling routine. 2. Register contents must always be saved and restored by word length, starting from an even-numbered address. 3. Ignored when returning from the interrupt handling routine.
Figure 3.2 Stack Status after Exception Handling 3.4.4 Interrupt Response Time
Table 3.2 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. Table 3.2
Item Waiting time for completion of executing instruction* Saving of PC and CCR to stack Vector fetch Instruction fetch Internal processing Note: * Not including EEPMOV instruction.
Interrupt Wait States
States 1 to 23 4 2 4 4 Total 15 to 37
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Interrupt is accepted
Interrupt level decision and wait for end of instruction Instruction prefetch Internal processing
Stack access
Vector fetch
Prefetch instruction of Internal interrupt-handling routine processing
Interrupt request signal
Internal address bus
(1)
(3)
(5) (6)
(8)
(9)
Internal read signal
Internal write signal (2)
(4)
(1)
(7)
Figure 3.3 Interrupt Sequence
(9)
Internal data bus (16 bits)
(10)
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(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) (2)(4) Instruction code (not executed) (3) Instruction prefetch address (Instruction is not executed.) (5) SP - 2 (6) SP - 4 (7) CCR (8) Vector address (9) Starting address of interrupt-handling routine (contents of vector) (10) First instruction of interrupt-handling routine
Section 3 Exception Handling
REJ09B0028-0500
Section 3 Exception Handling
3.5
3.5.1
Usage Notes
Interrupts after Reset
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.W #xx: 16, SP). 3.5.2 Notes on Stack Area Use
When word data is accessed, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @-SP) or POP Rn (MOV.W @SP+, Rn) to save or restore register values. 3.5.3 Notes on Rewriting Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins, IRQ3 to IRQ0, and WKP5 to WKP0, the interrupt request flag may be set to 1. When switching a pin function, mask the interrupt before setting the bit in the port mode register. After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0. Figure 3.4 shows a port mode register setting and interrupt request flag clearing procedure.
Interrupts masked. (Another possibility is to disable the relevant interrupt in interrupt enable register 1.)
CCR I bit 1
Set port mode register bit Execute NOP instruction Clear interrupt request flag to 0 After setting the port mode register bit, first execute at least one instruction (e.g., NOP), then clear the interrupt request flag to 0.
CCR I bit 0
Interrupt mask cleared
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure
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Section 4 Address Break
Section 4 Address Break
The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address. With the address break function, the execution start point of a program containing a bug is detected and execution is branched to the correcting program. Figure 4.1 shows a block diagram of the address break.
Internal address bus
Comparator
BARH Interrupt generation control circuit BDRH
BARL ABRKCR ABRKSR BDRL Internal data bus Interrupt
Comparator
[Legend] BARH, BARL: BDRH, BDRL: ABRKCR: ABRKSR:
Break address register Break data register Address break control register Address break status register
Figure 4.1 Block Diagram of Address Break
4.1
Register Descriptions
Address break has the following registers. * * * * Address break control register (ABRKCR) Address break status register (ABRKSR) Break address register (BARH, BARL) Break data register (BDRH, BDRL)
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ABK0001A_000020020200
Section 4 Address Break
4.1.1
Address Break Control Register (ABRKCR)
ABRKCR sets address break conditions.
Bit 7 Bit Name RTINTE Initial Value 1 R/W R/W Description RTE Interrupt Enable When this bit is 0, the interrupt immediately after executing RTE is masked and then one instruction must be executed. When this bit is 1, the interrupt is not masked. 6 5 CSEL1 CSEL0 0 0 R/W R/W Condition Select 1 and 0 These bits set address break conditions. 00: Instruction execution cycle 01: CPU data read cycle 10: CPU data write cycle 11: CPU data read/write cycle 4 3 2 ACMP2 ACMP1 ACMP0 0 0 0 R/W R/W R/W Address Compare Condition Select 2 to 0 These bits set the comparison condition between the address set in BAR and the internal address bus. 000: Compares 16-bit addresses 001: Compares upper 12-bit addresses 010: Compares upper 8-bit addresses 011: Compares upper 4-bit addresses 1XX: Reserved (setting prohibited) 1 0 DCMP1 DCMP0 0 0 R/W R/W Data Compare Condition Select 1 and 0 These bits set the comparison condition between the data set in BDR and the internal data bus. 00: No data comparison 01: Compares lower 8-bit data between BDRL and data bus 10: Compares upper 8-bit data between BDRH and data bus 11: Compares 16-bit data between BDR and data bus Legend: X: Don't care.
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Section 4 Address Break
When an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of the byte/word access and address. Table 4.1 shows the access and data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a byte access is generated twice. For details on data widths of each register, see section 20.1, Register Addresses (Address Order). Table 4.1 Access and Data Bus Used
Word Access Even Address Odd Address ROM space RAM space Upper 8 bits Upper 8 bits Lower 8 bits Lower 8 bits Upper 8 bits Lower 8 bits Byte Access Even Address Odd Address Upper 8 bits Upper 8 bits Upper 8 bits -- Upper 8 bits Upper 8 bits Upper 8 bits --
I/O register with 8-bit data bus Upper 8 bits width I/O register with 16-bit data bus width Upper 8 bits
4.1.2
Address Break Status Register (ABRKSR)
ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.
Bit 7 Bit Name ABIF Initial Value 0 R/W R/W Description Address Break Interrupt Flag [Setting condition] When the condition set in ABRKCR is satisfied [Clearing condition] When 0 is written after ABIF=1 is read 6 ABIE 0 R/W Address Break Interrupt Enable When this bit is 1, an address break interrupt request is enabled. 5 to 0 -- All 1 -- Reserved These bits are always read as 1.
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Section 4 Address Break
4.1.3
Break Address Registers (BARH, BARL)
BARH and BARL are 16-bit read/write registers that set the address for generating an address break interrupt. When setting the address break condition to the instruction execution cycle, set the first byte address of the instruction. The initial value of this register is H'FFFF. 4.1.4 Break Data Registers (BDRH, BDRL)
BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for even and odd addresses in the data transmission. Therefore, comparison data must be set in BDRH for byte access. For word access, the data bus used depends on the address. See section 4.1.1, Address Break Control Register (ABRKCR), for details. The initial value of this register is undefined.
4.2
Operation
When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt request is accepted, interrupt exception handling starts after the instruction being executed ends. The address break interrupt is not masked by the I bit in CCR of the CPU.
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Section 4 Address Break
Figures 4.2 show the operation examples of the address break interrupt setting.
When the address break is specified in instruction execution cycle
Register setting * ABRKCR = H'80 * BAR = H'025A
Program 0258 * 025A 025C 0260 0262 :
NOP NOP MOV.W @H'025A,R0 NOP NOP :
Underline indicates the address to be stacked.
NOP NOP MOV MOV instruc- instruc- instruc- instruction tion tion 1 tion 2 Internal prefetch prefetch prefetch prefetch processing
Stack save
Address bus Interrupt request
0258
025A
025C
025E
SP-2
SP-4
Interrupt acceptance
Figure 4.2 Address Break Interrupt Operation Example (1)
When the address break is specified in the data read cycle
Register setting * ABRKCR = H'A0 * BAR = H'025A
Program 0258 025A * 025C 0260 0262 :
NOP NOP MOV.W @H'025A,R0 NOP Underline indicates the address NOP to be stacked. :
MOV NOP MOV NOP Next MOV instruc- instruc- instruc- instruc- instruc- instrution 2 tion tion tion ction Internal Stack tion 1 prefetch prefetch prefetch execution prefetch prefetch processing save
Address bus Interrupt request
025C
025E
0260
025A
0262
0264
SP-2
Interrupt acceptance
Figure 4.2 Address Break Interrupt Operation Example (2)
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Section 4 Address Break
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Section 5 Clock Pulse Generators
Section 5 Clock Pulse Generators
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator, a duty correction circuit, and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. Figure 5.1 shows a block diagram of the clock pulse generators.
OSC1 OSC2
System clock oscillator
OSC (fOSC)
Duty correction circuit
OSC (fOSC)
System clock divider
OSC OSC/8 OSC/16 OSC/32 OSC/64
System clock pulse generator W/2 W (fW) Subclock divider W/4 W/8
Prescaler S (13 bits)
/2 to /8192
X1 X2
Subclock oscillator
SUB Prescaler W (5 bits) W/8 to W/128
Subclock pulse generator
Figure 5.1 Block Diagram of Clock Pulse Generators The basic clock signals that drive the CPU and on-chip peripheral modules are and SUB. The system clock is divided by prescaler S to become a clock signal from /8192 to /2, and the subclock is divided by prescaler W to become a clock signal from w/128 to w/8. Both the system clock and subclock signals are provided to the on-chip peripheral modules.
CPG0200A_000020020200
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Section 5 Clock Pulse Generators
5.1
System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing external clock input. Figure 5.2 shows a block diagram of the system clock generator.
OSC 2
LPM
OSC 1
LPM: Low-power mode (standby mode, subactive mode, subsleep mode)
Figure 5.2 Block Diagram of System Clock Generator 5.1.1 Connecting Crystal Resonator
Figure 5.3 shows a typical method of connecting a crystal resonator. An AT-cut parallel-resonance crystal resonator should be used. Figure 5.4 shows the equivalent circuit of a crystal resonator. A resonator having the characteristics given in table 5.1 should be used.
C1 OSC 1 OSC 2 C2 C1 = C 2 = 10 to 22 pF
Figure 5.3 Typical Connection to Crystal Resonator
LS
RS
CS
OSC 1
C0
OSC 2
Figure 5.4 Equivalent Circuit of Crystal Resonator
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Section 5 Clock Pulse Generators
Table 5.1
Crystal Resonator Parameters
2 500 7 pF 4 120 7 pF 8 80 7 pF 10 60 7 pF 16 50 7 pF 20 40 7 pF
Frequency (MHz) RS (max) C0 (max)
5.1.2
Connecting Ceramic Resonator
Figure 5.5 shows a typical method of connecting a ceramic resonator.
C1 OSC1 C2 OSC2 C1 = 5 to 30 pF C2 = 5 to 30 pF
Figure 5.5 Typical Connection to Ceramic Resonator 5.1.3 External Clock Input Method
Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 5.6 shows a typical connection. The duty cycle of the external clock signal must be 45 to 55%.
OSC1
External clock input
OSC 2
Open
Figure 5.6 Example of External Clock Input
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Section 5 Clock Pulse Generators
5.2
Subclock Generator
Figure 5.7 shows a block diagram of the subclock generator.
X2
8M
X1
Note : Registance is a reference value.
Figure 5.7 Block Diagram of Subclock Generator 5.2.1 Connecting 32.768-kHz Crystal Resonator
Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal resonator, as shown in figure 5.8. Figure 5.9 shows the equivalent circuit of the 32.768-kHz crystal resonator.
C1 X1 C2 X2 C1 = C 2 = 15 pF (typ.)
Figure 5.8 Typical Connection to 32.768-kHz Crystal Resonator
LS CS RS
X1 CO
X2
CO = 1.5 pF (typ.) RS = 14 k (typ.) fW = 32.768 kHz Note: Constants are reference values.
Figure 5.9 Equivalent Circuit of 32.768-kHz Crystal Resonator
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Section 5 Clock Pulse Generators
5.2.2
Pin Connection when Not Using Subclock
When the subclock is not used, connect pin X1 to VCL or VSS and leave pin X2 open, as shown in figure 5.10.
VCL or VSS X1
X2
Open
Figure 5.10 Pin Connection when not Using Subclock
5.3
5.3.1
Prescalers
Prescaler S
Prescaler S is a 13-bit counter using the system clock () as its input clock. It is incremented once per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state. In standby mode, subactive mode, and subsleep mode, the system clock pulse generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write prescaler S. The output from prescaler S is shared by the on-chip peripheral modules. The divider ratio can be set separately for each on-chip peripheral function. In active mode and sleep mode, the clock input to prescaler S is determined by the division factor designated by MA2 to MA0 in SYSCR2. 5.3.2 Prescaler W
Prescaler W is a 5-bit counter using a 32.768 kHz signal divided by 4 (W/4) as its input clock. The divided output is used for clock time base operation of timer A. Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state. Even in standby mode, subactive mode, or subsleep mode, prescaler W continues functioning so long as clock signals are supplied to pins X1 and X2. Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register A (TMA).
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Section 5 Clock Pulse Generators
5.4
5.4.1
Usage Notes
Note on Resonators
Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit constants will differ depending on the resonator element, stray capacitance in its interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the resonator element manufacturer. Design the circuit so that the resonator element never receives voltages exceeding its maximum rating. 5.4.2 Notes on Board Design
When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as close as possible to the OSC1 and OSC2 pins. Other signal lines should be routed away from the resonator circuit to prevent induction from interfering with correct oscillation (see figure 5.11).
Avoid
Signal A
Signal B
C1 OSC1 C2 OSC2
Figure 5.11 Example of Incorrect Board Design
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Section 6 Power-Down Modes
Section 6 Power-Down Modes
This LSI has six modes of operation after a reset. These include a normal active mode and four power-down modes, in which power consumption is significantly reduced. Module standby mode reduces power consumption by selectively halting on-chip module functions. * Active mode The CPU and all on-chip peripheral modules are operable on the system clock. The system clock frequency can be selected from osc, osc/8, osc/16, osc/32, and osc/64. * Subactive mode The CPU and all on-chip peripheral modules are operable on the subclock. The subclock frequency can be selected from w/2, w/4, and w/8. * Sleep mode The CPU halts. On-chip peripheral modules are operable on the system clock. * Subsleep mode The CPU halts. On-chip peripheral modules are operable on the subclock. * Standby mode The CPU and all on-chip peripheral modules halt. When the clock time-base function is selected, timer A is operable. * Module standby mode Independent of the above modes, power consumption can be reduced by halting on-chip peripheral modules that are not used in module units.
6.1
Register Descriptions
The registers related to power-down modes are listed below. * System control register 1 (SYSCR1) * System control register 2 (SYSCR2) * Module standby control register 1 (MSTCR1)
LPW3003A_000020020200
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Section 6 Power-Down Modes
6.1.1
System Control Register 1 (SYSCR1)
SYSCR1 controls the power-down modes, as well as SYSCR2.
Bit 7 Bit Name SSBY Initial Value 0 R/W R/W Description Software Standby This bit selects the mode to transit after the execution of the SLEEP instruction. 0: a transition is made to sleep mode or subsleep mode. 1: a transition is made to standby mode. For details, see table 6.2. 6 5 4 STS2 STS1 STS0 0 0 0 R/W R/W R/W Standby Timer Select 2 to 0 These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode, subactive mode, or subsleep mode to active mode or sleep mode due to an interrupt. The designation should be made according to the clock frequency so that the waiting time is at least 6.5 ms. The relationship between the specified value and the number of wait states is shown in table 6.1. When an external clock is to be used, the minimum value (STS2 = STS1 = STS0 = 1) is recommended. Noise Elimination Sampling Frequency Select The subclock pulse generator generates the watch clock signal (W) and the system clock pulse generator generates the oscillator clock (OSC). This bit selects the sampling frequency of the oscillator clock when the watch clock signal (W) is sampled. When OSC = 4 to 20 MHz, clear NESEL to 0. 0: Sampling rate is OSC/16 1: Sampling rate is OSC/4 2 to 0 All 0 Reserved These bits are always read as 0.
3
NESEL
0
R/W
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Section 6 Power-Down Modes
Table 6.1
Operating Frequency and Waiting Time
20 MHz 0.4 0.8 1.6 3.3 6.6 0.05 0.00 0.00 16 MHz 0.5 1.0 2.0 4.1 8.2 0.06 0.00 0.00 10 MHz 0.8 1.6 3.3 6.6 13.1 0.10 0.01 0.00 8 MHz 1.0 2.0 4.1 8.2 16.4 0.13 0.02 0.00 4 MHz 2.0 4.1 8.2 16.4 32.8 0.26 0.03 0.00 2 MHz 4.1 8.2 16.4 32.8 65.5 0.51 0.06 0.01 1 MHz 0.5 MHz 8.1 16.4 32.8 65.5 131.1 1.02 0.13 0.02 16.4 32.8 65.5 131.1 262.1 2.05 0.26 0.03
STS2 STS1 STS0 Waiting Time 0 0 0 1 1 0 1 1 0 0 1 1 0 1 8,192 states 16,384 states 32,768 states 65,536 states 131,072 states 1,024 states 128 states 16 states
Note: Time unit is ms.
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Section 6 Power-Down Modes
6.1.2
System Control Register 2 (SYSCR2)
SYSCR2 controls the power-down modes, as well as SYSCR1.
Bit 7 6 5 Bit Name SMSEL LSON DTON Initial Value 0 0 0 R/W R/W R/W R/W Description Sleep Mode Selection Low Speed on Flag Direct Transfer on Flag These bits select the mode to transit after the execution of a SLEEP instruction, as well as bit SSBY of SYSCR1. For details, see table 6.2. 4 3 2 MA2 MA1 MA0 0 0 0 R/W R/W R/W Active Mode Clock Select 2 to 0 These bits select the operating clock frequency in active and sleep modes. The operating clock frequency changes to the set frequency after the SLEEP instruction is executed. 0XX: OSC 100: OSC/8 101: OSC/16 110: OSC/32 111: OSC/64 1 0 SA1 SA0 0 0 R/W R/W Subactive Mode Clock Select 1 and 0 These bits select the operating clock frequency in subactive and subsleep modes. The operating clock frequency changes to the set frequency after the SLEEP instruction is executed. 00: W/8 01: W/4 1X: W/2 Legend: X : Don't care.
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Section 6 Power-Down Modes
6.1.3
Module Standby Control Register 1 (MSTCR1)
MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units.
Bit 7 6 5 4 Bit Name MSTIIC MSTS3 MSTAD Initial Value 0 0 0 0 R/W R/W R/W R/W Description Reserved This bit is always read as 0. IIC Module Standby IIC enters standby mode when this bit is set to 1 SCI3 Module Standby SCI3 enters standby mode when this bit is set to 1 A/D Converter Module Standby A/D converter enters standby mode when this bit is set to 1 3 MSTWD 0 R/W Watchdog Timer Module Standby Watchdog timer enters standby mode when this bit is set to 1.When the internal oscillator is selected for the watchdog timer clock, the watchdog timer operates regardless of the setting of this bit 2 1 0 MSTTW MSTTV MSTTA 0 0 0 R/W R/W R/W Timer W Module Standby Timer W enters standby mode when this bit is set to 1 Timer V Module Standby Timer V enters standby mode when this bit is set to 1 Timer A Module Standby Timer A enters standby mode when this bit is set to 1
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Section 6 Power-Down Modes
6.2
Mode Transitions and States of LSI
Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing a SLEEP instruction. Interrupts allow for returning from the program halt state to the program execution state of the program. A direct transition between active mode and subactive mode, which are both program execution states, can be made without halting the program. The operating frequency can also be changed in the same modes by making a transition directly from active mode to active mode, and from subactive mode to subactive mode. RES input enables transitions from a mode to the reset state. Table 6.2 shows the transition conditions of each mode after the SLEEP instruction is executed and a mode to return by an interrupt. Table 6.3 shows the internal states of the LSI in each mode.
Reset state Program halt state SLEEP instruction Standby mode Interrupt Active mode Interrupt SLEEP instruction Direct transition interrupt SLEEP instruction SLEEP instruction Interrupt Direct transition interrupt Interrupt Program execution state Direct transition interrupt SLEEP instruction Sleep mode Program halt state
SLEEP instruction Subactive mode Subsleep mode Interrupt
Direct transition interrupt Notes: 1. To make a transition to another mode by an interrupt, make sure interrupt handling is after the interrupt is accepted. 2. Details on the mode transition conditions are given in table 6.2.
Figure 6.1 Mode Transition Diagram
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Table 6.2
Transition Mode after SLEEP Instruction Execution and Interrupt Handling
Transition Mode after SLEEP Instruction Execution Sleep mode Transition Mode due to Interrupt Active mode Subactive mode Subsleep mode Active mode Subactive mode Standby mode Active mode (direct transition) Subactive mode (direct transition) Active mode -- --
DTON 0
SSBY 0
SMSEL 0
LSON 0 1
1
0 1
1 1 X X Legend: *
X 0* X
X 0 1
X : Don't care. When a state transition is performed while SMSEL is 1, timer V, SCI3, and the A/D converter are reset, and all registers are set to their initial values. To use these functions after entering active mode, reset the registers.
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Table 6.3
Function
Internal State in Each Operating Mode
Active Mode Functioning Functioning Functioning Functioning Functioning Functioning Sleep Mode Functioning Functioning Halted Retained Retained Retained Subactive Mode Halted Functioning Functioning Functioning Functioning Functioning Subsleep Mode Halted Functioning Halted Retained Retained Retained Standby Mode Halted Functioning Halted Retained Retained Register contents are retained, but output is the highimpedance state. Functioning Functioning
System clock oscillator Subclock oscillator CPU operations RAM IO ports Instructions Registers
External interrupts
IRQ3 to IRQ0 WKP5 to WKP0 Timer A Timer V Timer W
Functioning Functioning Functioning Functioning Functioning
Functioning Functioning Functioning Functioning Functioning
Functioning Functioning
Functioning Functioning
Peripheral functions
Functioning if the timekeeping time-base function is selected, and retained if not selected Reset Reset Reset Retained
Retained (if internal clock is selected as a count clock, the counter is incremented by a subclock*)
Watchdog timer SCI3 IIC A/D converter
Functioning Functioning Functioning Functioning
Functioning Functioning Functioning Functioning
Retained (functioning if the internal oscillator is selected as a count clock*) Reset Retained* Reset Reset Retained Reset Reset Retained Reset
Note:
*
Registers can be read or written in subactive mode.
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6.2.1
Sleep Mode
In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2, MA1, and MA0 bits in SYSCR2. CPU register contents are retained. When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the requested interrupt is disabled in the interrupt enable register. After sleep mode is cleared, a transition is made to active mode when the LSON bit in SYSCR2 is 0, and a transition is made to subactive mode when the bit is 1. When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared. 6.2.2 Standby Mode
In standby mode, the clock pulse generator stops, so the CPU and on-chip peripheral modules stop functioning. However, as long as the rated voltage is supplied, the contents of CPU registers, onchip RAM, and some on-chip peripheral module registers are retained. On-chip RAM contents will be retained as long as the voltage set by the RAM data retention voltage is provided. The I/O ports go to the high-impedance state. Standby mode is cleared by an interrupt. When an interrupt is requested, the system clock pulse generator starts. After the time set in bits STS2-STS0 in SYSCR1 has elapsed, and interrupt exception handling starts. Standby mode is not cleared if the I bit of CCR is set to 1 or the requested interrupt is disabled in the interrupt enable register. When the RES pin goes low, the system clock pulse generator starts. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator output has stabilized, the CPU starts reset exception handling if the RES pin is driven high. 6.2.3 Subsleep Mode
In subsleep mode, operation of the CPU and on-chip peripheral modules other than timer A is halted. As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM, and some registers of the on-chip peripheral modules are retained. I/O ports keep the same states as before the transition. Subsleep mode is cleared by an interrupt. When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. Subsleep mode is not cleared if the I bit of CCR is set to 1 or the requested interrupt is disabled in the interrupt enable register. After subsleep mode is
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Section 6 Power-Down Modes
cleared, a transition is made to active mode when the LSON bit in SYSCR2 is 0, and a transition is made to subactive mode when the bit is 1. When the RES pin goes low, the system clock pulse generator starts. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator output has stabilized, the CPU starts reset exception handling if the RES pin is driven high. 6.2.4 Subactive Mode
The operating frequency of subactive mode is selected from W/2, W/4, and W/8 by the SA1 and SA0 bits in SYSCR2. After the SLEEP instruction is executed, the operating frequency changes to the frequency which is set before the execution. When the SLEEP instruction is executed in subactive mode, a transition to sleep mode, subsleep mode, standby mode, active mode, or subactive mode is made, depending on the combination of SYSCR1 and SYSCR2. When the RES pin goes low, the system clock pulse generator starts. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
6.3
Operating Frequency in Active Mode
Operation in active mode is clocked at the frequency designated by the MA2, MA1, and MA0 bits in SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction execution.
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6.4
Direct Transition
The CPU can execute programs in two modes: active and subactive mode. A direct transition is a transition between these two modes without stopping program execution. A direct transition can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. The direct transition also enables operating frequency modification in active or subactive mode. After the mode transition, direct transition interrupt exception handling starts. If the direct transition interrupt is disabled in interrupt enable register 1, a transition is made instead to sleep or subsleep mode. Note that if a direct transition is attempted while the I bit in CCR is set to 1, sleep or subsleep mode will be entered, and the resulting mode cannot be cleared by means of an interrupt. 6.4.1 Direct Transition from Active Mode to Subactive Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (1). Direct transition time = {(number of SLEEP instruction execution states) + (number of internal processing states)}x (tcyc before transition) + (number of interrupt exception handling states) x (tsubcyc after transition) (1) Example Direct transition time = (2 + 1) x tosc + 14 x 8tw = 3tosc + 112tw (when the CPU operating clock of osc w/8 is selected) Legend tosc: OSC clock cycle time tw: watch clock cycle time tcyc: system clock () cycle time tsubcyc: subclock (SUB) cycle time 6.4.2 Direct Transition from Subactive Mode to Active Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2). Direct transition time = {(number of SLEEP instruction execution states) + (number of internal processing states)} x (tsubcyc before transition) + {(waiting time set in bits STS2 to STS0) + (number of interrupt exception handling states)} x (tcyc after transition) (2)
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Example Direct transition time = (2 + 1) x 8tw + (8192 + 14) x tosc = 24tw + 8206tosc (when the CPU operating clock of w/8 osc and a waiting time of 8192 states are selected) Legend tosc: OSC clock cycle time tw: watch clock cycle time tcyc: system clock () cycle time tsubcyc: subclock (SUB) cycle time
6.5
Module Standby Function
The module-standby function can be set to any peripheral module. In module standby mode, the clock supply to modules stops to enter the power-down mode. Module standby mode enables each on-chip peripheral module to enter the standby state by setting a bit that corresponds to each module to 1 and cancels the mode by clearing the bit to 0.
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Section 7 ROM
The features of the 32-kbyte flash memory built into the flash memory version are summarized below. * Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is configured as follows: 1 kbyte x 4 blocks and 28 kbytes x 1 block. To erase the entire flash memory, each block must be erased in turn. * Reprogramming capability The flash memory can be reprogrammed up to 1,000 times. * On-board programming On-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. In normal user program mode, individual blocks can be erased or programmed. * Programmer mode Flash memory can be programmed/erased in programmer mode using a PROM programmer, as well as in on-board programming mode. * Automatic bit rate adjustment For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. * Programming/erasing protection Sets software protection against flash memory programming/erasing. * Power-down mode Operation of the power supply circuit can be partly halted in subactive mode. As a result, flash memory can be read with low power consumption.
7.1
Block Configuration
Figure 7.1 shows the block configuration of 32-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 1 kbyte x 4 blocks and 28 kbytes x 1 block. Erasing is performed in these units. Programming is performed in 128-byte units starting from an address with lower eight bits H'00 or H'80.
ROM3321A_000120030300
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H'0000
Erase unit 1kbyte
H'0001 H'0081
H'0002 H'0082
Programming unit: 128 bytes
H'007F H'00FF
H'0080
H'0380 H'0400
Erase unit 1kbyte
H'0381 H'0401 H'0481
H'0382 H'0402 H'0481
Programming unit: 128 bytes
H'03FF H'047F H'04FF
H'0480
H'0780 H'0800
Erase unit 1kbyte
H'0781 H'0801 H'0881
H'0782 H'0802 H'0882
Programming unit: 128 bytes
H'07FF H'087F H'08FF
H'0880
H'0B80 H'0C00
Erase unit 1kbyte
H'0B81 H'0C01 H'0C81
H'0B82 H'0C02 H'0C82
Programming unit: 128 bytes
H'0BFF H'0C7F H'0CFF
H'0C80
H'0F80 H'1000
Erase unit 28 kbytes
H'0F81 H'1001 H'1081
H'0F82 H'1002 H'1082
Programming unit: 128 bytes
H'0FFF H'107F H'10FF
H'1080
H'7F80
H'7F81
H'7F82
H'7FFF
Figure 7.1 Flash Memory Block Configuration
7.2
Register Descriptions
The flash memory has the following registers. * * * * * Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Erase block register 1 (EBR1) Flash memory power control register (FLPWCR) Flash memory enable register (FENR)
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Section 7 ROM
7.2.1
Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 7.4, Flash Memory Programming/Erasing.
Bit 7 6 Bit Name -- SWE Initial Value 0 0 R/W -- R/W Description Reserved This bit is always read as 0. Software Write Enable When this bit is set to 1, flash memory programming/erasing is enabled. When this bit is cleared to 0, other FLMCR1 register bits and all EBR1 bits cannot be set. 5 ESU 0 R/W Erase Setup When this bit is set to 1, the flash memory changes to the erase setup state. When it is cleared to 0, the erase setup state is cancelled. Set this bit to 1 before setting the E bit to 1 in FLMCR1. 4 PSU 0 R/W Program Setup When this bit is set to 1, the flash memory changes to the program setup state. When it is cleared to 0, the program setup state is cancelled. Set this bit to 1 before setting the P bit in FLMCR1. 3 EV 0 R/W Erase-Verify When this bit is set to 1, the flash memory changes to erase-verify mode. When it is cleared to 0, erase-verify mode is cancelled. 2 PV 0 R/W Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, programverify mode is cancelled. 1 E 0 R/W Erase When this bit is set to 1, and while the SWE=1 and ESU=1 bits are 1, the flash memory changes to erase mode. When it is cleared to 0, erase mode is cancelled.
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Bit 0
Bit Name P
Initial Value 0
R/W R/W
Description Program When this bit is set to 1, and while the SWE=1 and PSU=1 bits are 1, the flash memory changes to program mode. When it is cleared to 0, program mode is cancelled.
7.2.2
Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to.
Bit 7 Bit Name FLER Initial Value 0 R/W R Description Flash Memory Error Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state. See 7.5.3, Error Protection, for details. 6 to 0 -- All 0 -- Reserved These bits are always read as 0.
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7.2.3
Erase Block Register 1 (EBR1)
EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to be automatically cleared to 0.
Bit 7 to 5 4 3 2 1 0 Bit Name -- EB4 EB3 EB2 EB1 EB0 Initial Value All 0 0 0 0 0 0 R/W -- R/W R/W R/W R/W R/W Description Reserved These bits are always read as 0. When this bit is set to 1, 28 kbytes of H'1000 to H'7FFF will be erased. When this bit is set to 1, 1 kbyte of H'0C00 to H'0FFF will be erased. When this bit is set to 1, 1 kbyte of H'0800 to H'0BFF will be erased. When this bit is set to 1, 1 kbyte of H'0400 to H'07FF will be erased. When this bit is set to 1, 1 kbyte of H'0000 to H'03FF will be erased.
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7.2.4
Flash Memory Power Control Register (FLPWCR)
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. There are two modes: mode in which operation of the power supply circuit of flash memory is partly halted in power-down mode and flash memory can be read, and mode in which even if a transition is made to subactive mode, operation of the power supply circuit of flash memory is retained and flash memory can be read.
Bit 7 Bit Name PDWND Initial Value 0 R/W R/W Description Power-Down Disable When this bit is 0 and a transition is made to subactive mode, the flash memory enters the power-down mode. When this bit is 1, the flash memory remains in the normal mode even after a transition is made to subactive mode. 6 to 0 -- All 0 -- Reserved These bits are always read as 0.
7.2.5
Flash Memory Enable Register (FENR)
Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR1, and FLPWCR.
Bit 7 Bit Name FLSHE Initial Value 0 R/W R/W Description Flash Memory Control Register Enable Flash memory control registers can be accessed when this bit is set to 1. Flash memory control registers cannot be accessed when this bit is set to 0. 6 to 0 -- All 0 -- Reserved These bits are always read as 0.
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Section 7 ROM
7.3
On-Board Programming Modes
There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST pin settings, NMI pin settings, and input level of each port, as shown in table 7.1. The input level of each pin must be defined four states before the reset ends. When changing to boot mode, the boot program built into this LSI is initiated. The boot program transfers the programming control program from the externally-connected host to on-chip RAM via SCI3. After erasing the entire flash memory, the programming control program is executed. This can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. In user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. Table 7.1
TEST 0 0 1
Setting Programming Modes
NMI 1 0 X P85 X 1 X PB0 X X 0 PB1 X X 0 PB2 X X 0 LSI State after Reset End User Mode Boot Mode Programmer Mode
Legend: X : Don't care.
7.3.1
Boot Mode
Table 7.2 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 7.4, Flash Memory Programming/Erasing. 2. SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3. When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be
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Section 7 ROM
4.
5.
6.
7.
8.
pulled up on the board if necessary. After the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the completion of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could not be performed normally, initiate boot mode again by a reset. Depending on the host's transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate and system clock frequency of this LSI within the ranges listed in table 7.3. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'F780 to H'FEEF is the area to which the programming control program is transferred from the host. The boot program area cannot be used until the execution state in boot mode switches to the programming control program. Before branching to the programming control program, the chip terminates transfer operations by SCI3 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value remains set in BRR. Therefore, the programming control program can still use it for transfer of write data or verify data with the host. The TxD pin is high (PCR22 = 1, P22 = 1). The contents of the CPU general registers are undefined immediately after branching to the programming control program. These registers must be initialized at the beginning of the programming control program, as the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at least 20 states, and then setting the NMI pin. Boot mode is also cleared when a WDT overflow occurs. Do not change the TEST pin and NMI pin input levels in boot mode.
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Section 7 ROM
Table 7.2
Item
Boot Mode Operation
Host Operation Processing Contents Communication Contents LSI Operation Processing Contents Branches to boot program at reset-start.
Boot mode initiation
Boot program initiation
Bit rate adjustment
Continuously transmits data H'00 at specified bit rate.
H'00, H'00 . . . H'00
Transmits data H'55 when data H'00 is received error-free.
H'00
* Measures low-level period of receive data H'00. * Calculates bit rate and sets BRR in SCI3. * Transmits data H'00 to host as adjustment end indication. H'55 reception.
H'55
Flash memory erase
Boot program erase error
H'FF
H'AA reception
H'AA
Checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data H'AA to host. (If erase could not be done, transmits data H'FF to host and aborts operation.)
Transfer of number of bytes of programming control program
Transmits number of bytes (N) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte)
Upper bytes, lower bytes Echoback
Echobacks the 2-byte data received to host.
Transmits 1-byte of programming control program (repeated for N times)
H'XX
Echoback
Echobacks received data to host and also transfers it to RAM. (repeated for N times)
H'AA reception
H'AA
Transmits data H'AA to host.
Branches to programming control program transferred to on-chip RAM and starts execution.
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Section 7 ROM
Table 7.3
System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible
System Clock Frequency Range of LSI 16 to 20 MHz 8 to 16 MHz 4 to 16 MHz 2 to 16 MHz
Host Bit Rate 19,200 bps 9,600 bps 4,800 bps 2,400 bps
7.3.2
Programming/Erasing in User Program Mode
On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. As the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot mode. Figure 7.2 shows a sample procedure for programming/erasing in user program mode. Prepare a user program/erase control program in accordance with the description in section 7.4, Flash Memory Programming/Erasing.
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Reset-start
No
Program/erase?
Yes
Transfer user program/erase control program to RAM
Branch to flash memory application program
Branch to user program/erase control program in RAM
Execute user program/erase control program (flash memory rewrite)
Branch to flash memory application program
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode
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Section 7 ROM
7.4
Flash Memory Programming/Erasing
A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. Flash memory programming and erasing should be performed in accordance with the descriptions in section 7.4.1, Program/Program-Verify and section 7.4.2, Erase/Erase-Verify, respectively. 7.4.1 Program/Program-Verify
When writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 7.3 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. Programming must be done to an empty address. Do not reprogram an address to which programming has already been performed. 2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform reprogramming data computation according to table 7.4, and additional programming data computation according to table 7.5. 4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The program address and 128-byte data are latched in the flash memory. The lower 8 bits of the start address in the flash memory destination area must be H'00 or H'80. 5. The time during which the P bit is set to 1 is the programming time. Table 7.6 shows the allowable programming times. 6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. An overflow cycle of approximately 6.6 ms is allowed. 7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits are B'00. Verify data can be read in words or in longwords from the address to which a dummy write was performed.
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Section 7 ROM
8.
The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000.
Write pulse application subroutine
Apply Write Pulse WDT enable Set PSU bit in FLMCR1 Wait 50 s Set P bit in FLMCR1 Wait (Wait time=programming time) Clear P bit in FLMCR1 Wait 5 s Clear PSU bit in FLMCR1 Wait 5 s
Disable WDT
START Set SWE bit in FLMCR1 Wait 1 s
*
Store 128-byte program data in program data area and reprogram data area
n= 1 m= 0
Write 128-byte data in RAM reprogram data area consecutively to flash memory
Apply Write pulse Set PV bit in FLMCR1 Wait 4 s Set block start address as verify address
nn+1 H'FF dummy write to verify address
End Sub
Wait 2 s
Read verify data Increment address Verify data = write data?
*
No m=1 No
Yes n6?
Yes Additional-programming data computation
Reprogram data computation
No
128-byte data verification completed?
Yes Clear PV bit in FLMCR1 Wait 2 s n 6? Yes Successively write 128-byte data from additionalprogramming data area in RAM to flash memory Sub-Routine-Call Apply Write Pulse No Yes No
m= 0 ? Yes Clear SWE bit in FLMCR1 Wait 100 s
End of programming
n 1000 ?
No Clear SWE bit in FLMCR1 Wait 100 s
Programming failure
Notes: * The RTS instruction must not be used during the following 1. and 2. periods. 1. A period between 128-byte data programming to flash memory and the P bit clearing 2. A period between dummy writing of H'FF to a verify address and verify data reading
Figure 7.3 Program/Program-Verify Flowchart
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Section 7 ROM
Table 7.4
Reprogram Data Computation Table
Verify Data 0 1 0 1 Reprogram Data 1 0 1 1 Comments Programming completed Reprogram bit -- Remains in erased state
Program Data 0 0 1 1
Table 7.5
Additional-Program Data Computation Table
Verify Data 0 1 0 1 Additional-Program Data 0 1 1 1 Comments Additional-program bit No additional programming No additional programming No additional programming
Reprogram Data 0 0 1 1
Table 7.6
Programming Time
Programming Time 30 200 In Additional Programming 10 -- Comments
n (Number of Writes) 1 to 6 7 to 1,000
Note: Time shown in s.
7.4.2
Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR1). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An overflow cycle of approximately 19.8 ms is allowed.
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Section 7 ROM
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two bits are B'00. Verify data can be read in longwords from the address to which a dummy write was performed. 6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is 100. 7.4.3 Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. Interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. If interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the CPU malfunctions. 3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out.
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Section 7 ROM
Erase start SWE bit 1 Wait 1 s n1 Set EBR1 Enable WDT ESU bit 1 Wait 100 s E bit 1 Wait 10 ms E bit 0 Wait 10 s ESU bit 10 10 s Disable WDT EV bit 1 Wait 20 s
Set block start address as verify address
H'FF dummy write to verify address Wait 2 s Read verify data No Increment address Verify data + all 1s ? Yes
*
nn+1
No Last address of block ? Yes EV bit 0 Wait 4 s EV bit 0 Wait 4s
No
All erase block erased ? Yes Yes SWE bit 0 Wait 100 s End of erasing
n 100 ? No
Yes
SWE bit 0 Wait 100 s Erase failure
Note: *The RTS instruction must not be used during a period between dummy writing of H'FF to a verify address and verify data reading.
Figure 7.4 Erase/Erase-Verify Flowchart
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Section 7 ROM
7.5
Program/Erase Protection
There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), and erase block register 1 (EBR1) are initialized. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. 7.5.2 Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block register 1 (EBR1), erase protection can be set for individual blocks. When EBR1 is set to H'00, erase protection is set for all blocks. 7.5.3 Error Protection
In error protection, an error is detected when CPU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. When the following errors are detected during programming/erasing of flash memory, the FLER bit in FLMCR2 is set to 1, and the error protection state is entered. * When the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) * Immediately after exception handling excluding a reset during programming/erasing * When a SLEEP instruction is executed during programming/erasing The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be reRev.5.00 Nov. 02, 2005 Page 103 of 418 REJ09B0028-0500
Section 7 ROM
entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. Error protection can be cleared only by a reset.
7.6
Programmer Mode
In programmer mode, a PROM programmer can be used to perform programming/erasing via a socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU device type with the on-chip 64-kbyte flash memory (FZTAT64V5).
7.7
Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states: * Normal operating mode The flash memory can be read and written to at high speed. * Power-down operating mode The power supply circuit of flash memory can be partly halted. As a result, flash memory can be read with low power consumption. * Standby mode All flash memory circuits are halted. Table 7.7 shows the correspondence between the operating modes of this LSI and the flash memory. In subactive mode, the flash memory can be set to operate in power-down mode with the PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from power-down mode or standby mode, a period to stabilize operation of the power supply circuits that were stopped is needed. When the flash memory returns to its normal operating state, bits STS2 to STS0 in SYSCR1 must be set to provide a wait time of at least 20 s, even when the external clock is being used.
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Section 7 ROM
Table 7.7
Flash Memory Operating States
Flash Memory Operating State
LSI Operating State Active mode Subactive mode Sleep mode Subsleep mode Standby mode
PDWND = 0 (Initial value) Normal operating mode Power-down mode Normal operating mode Standby mode Standby mode
PDWND = 1 Normal operating mode Normal operating mode Normal operating mode Standby mode Standby mode
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Section 7 ROM
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Section 8 RAM
Section 8 RAM
This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data.
Product Classification Flash memory version (F-ZTATTM version) Mask-ROM version H8/3694F H8/3694 H8/3693 H8/3692 H8/3691 H8/3690 EEPROM stacked version Flash memory version Mask-ROM version Note: * H8/3694N RAM Size 2 kbytes 1 kbyte 1 kbyte 512 kbytes 512 kbytes 512 kbytes 2 kbytes RAM Address H'F780 to H'FF7F* H'FB80 to H'FF7F H'FB80 to H'FF7F H'FD80 to H'FF7F H'FD80 to H'FF7F H'FD80 to H'FF7F H'F780 to H'FF7F*
1 kbyte
H'FB80 to H'FF7F
When the E7 or E8 is used, area H'F780 to H'FB7F must not be accessed.
RAM0300A_000120030300
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Section 8 RAM
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Section 9 I/O Ports
Section 9 I/O Ports
The group of this LSI has twenty-nine general I/O ports (twenty-seven general I/O ports in the H8/3694N) and eight general input-only ports. Port 8 is a large current port, which can drive 20 mA (@VOL = 1.5 V) when a low level signal is output. Any of these ports can become an input port immediately after a reset. They can also be used as I/O pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings. The registers for selecting these functions can be divided into two types: those included in I/O ports and those included in each on-chip peripheral module. General I/O ports are comprised of the port control register for controlling inputs/outputs and the port data register for storing output data and can select inputs/outputs in bit units. For functions in each port, see appendix B.1, I/O Port Block Diagrams. For the execution of bit manipulation instructions to the port control register and port data register, see section 2.8.3, Bit Manipulation Instruction.
9.1
Port 1
Port 1 is a general I/O port also functioning as IRQ interrupt input pins, a timer A output pin, and a timer V input pin. Figure 9.1 shows its pin configuration.
P17/IRQ3/TRGV P16/IRQ2 P15/IRQ1
Port 1
P14/IRQ0 P12 P11 P10/TMOW
Figure 9.1 Port 1 Pin Configuration Port 1 has the following registers. * * * * Port mode register 1 (PMR1) Port control register 1 (PCR1) Port data register 1 (PDR1) Port pull-up control register 1 (PUCR1)
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9.1.1
Port Mode Register 1 (PMR1)
PMR1 switches the functions of pins in port 1 and port 2.
Bit 7 Bit Name IRQ3 Initial Value 0 R/W R/W Description P17/IRQ3/TRGV Pin Function Switch This bit selects whether pin P17/IRQ3/TRGV is used as P17 or as IRQ3/TRGV. 0: General I/O port 1: IRQ3/TRGV input pin 6 IRQ2 0 R/W P16/IRQ2 Pin Function Switch This bit selects whether pin P16/IRQ2 is used as P16 or as IRQ2. 0: General I/O port 1: IRQ2 input pin 5 IRQ1 0 R/W P15/IRQ1 Pin Function Switch This bit selects whether pin P15/IRQ1 is used as P15 or as IRQ1. 0: General I/O port 1: IRQ1 input pin 4 IRQ0 0 R/W P14/IRQ0 Pin Function Switch This bit selects whether pin P14/IRQ0 is used as P14 or as IRQ0. 0: General I/O port 1: IRQ0 input pin 3, 2 1 TXD All 1 0 R/W Reserved These bits are always read as 1. P22/TXD Pin Function Switch This bit selects whether pin P22/TXD is used as P22 or as TXD. 0: General I/O port 1: TXD output pin 0 TMOW 0 R/W P10/TMOW Pin Function Switch This bit selects whether pin P10/TMOW is used as P10 or as TMOW. 0: General I/O port 1: TMOW output pin
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Section 9 I/O Ports
9.1.2
Port Control Register 1 (PCR1)
PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR17 PCR16 PCR15 PCR14 PCR12 PCR11 PCR10 Initial Value 0 0 0 0 0 0 0 R/W W W W W W W W Description When the corresponding pin is designated in PMR1 as a general I/O pin, setting a PCR1 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Bit 3 is a reserved bit.
9.1.3
Port Data Register 1 (PDR1)
PDR1 is a general I/O port data register of port 1.
Bit 7 6 5 4 3 2 1 0 Bit Name P17 P16 P15 P14 P12 P11 P10 Initial Value 0 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description PDR1 stores output data for port 1 pins. If PDR1 is read while PCR1 bits are set to 1, the value stored in PDR1 are read. If PDR1 is read while PCR1 bits are cleared to 0, the pin states are read regardless of the value stored in PDR1. Bit 3 is a reserved bit. This bit is always read as 1.
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Section 9 I/O Ports
9.1.4
Port Pull-Up Control Register 1 (PUCR1)
PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports.
Bit 7 6 5 4 3 2 1 0 Bit Name PUCR17 PUCR16 PUCR15 PUCR14 PUCR12 PUCR11 PUCR10 Initial Value 0 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Only bits for which PCR1 is cleared are valid. The pull-up MOS of P17 to P14 and P12 to P10 pins enter the onstate when these bits are set to 1, while they enter the off-state when these bits are cleared to 0. Bit 3 is a reserved bit. This bit is always read as 1.
9.1.5
Pin Functions
The correspondence between the register specification and the port functions is shown below. P17/IRQ3/TRGV pin
Register Bit Name PMR1 IRQ3 PCR1 PCR17 0 1 1 Legend: X: Don't care. X Pin Function P17 input pin P17 output pin IRQ3 input/TRGV input pin
Setting value 0
P16/IRQ2 pin
Register Bit Name PMR1 IRQ2 PCR1 PCR16 0 1 1 Legend: X: Don't care. X Pin Function P16 input pin P16 output pin IRQ2 input pin
Setting value 0
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Section 9 I/O Ports
P15/IRQ1 pin
Register Bit Name PMR1 IRQ1 PCR1 PCR15 0 1 1 Legend: X: Don't care. X Pin Function P15 input pin P15 output pin IRQ1 input pin
Setting value 0
P14/IRQ0 pin
Register Bit Name PMR1 IRQ0 PCR1 PCR14 0 1 1 Legend: X: Don't care. X Pin Function P14 input pin P14 output pin IRQ0 input pin
Setting value 0
P12 pin
Register Bit Name Setting value PCR1 PCR12 0 1 Pin Function P12 input pin P12 output pin
P11 pin
Register Bit Name Setting value PCR1 PCR11 0 1 Pin Function P11 input pin P11 output pin
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Section 9 I/O Ports
P10/TMOW pin
Register Bit Name PMR1 TMOW PCR1 PCR10 0 1 1 Legend: X: Don't care. X Pin Function P10 input pin P10 output pin TMOW output pin
Setting value 0
9.2
Port 2
Port 2 is a general I/O port also functioning as a SCI3 I/O pin. Each pin of the port 2 is shown in figure 9.2. The register settings of PMR1 and SCI3 have priority for functions of the pins for both uses.
P22/TXD Port 2 P21/RXD P20/SCK3
Figure 9.2 Port 2 Pin Configuration Port 2 has the following registers. * Port control register 2 (PCR2) * Port data register 2 (PDR2)
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Section 9 I/O Ports
9.2.1
Port Control Register 2 (PCR2)
PCR2 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 2.
Bit 7 to 3 2 1 0 Bit Name PCR22 PCR21 PCR20 Initial Value 0 0 0 R/W W W W Description Reserved When each of the port 2 pins P22 to P20 functions as an general I/O port, setting a PCR2 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
9.2.2
Port Data Register 2 (PDR2)
PDR2 is a general I/O port data register of port 2.
Bit 7 to 3 2 1 0 Bit Name P22 P21 P20 Initial Value All 1 0 0 0 R/W R/W R/W R/W Description Reserved These bits are always read as 1. PDR2 stores output data for port 2 pins. If PDR2 is read while PCR2 bits are set to 1, the value stored in PDR2 is read. If PDR2 is read while PCR2 bits are cleared to 0, the pin states are read regardless of the value stored in PDR2.
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Section 9 I/O Ports
9.2.3
Pin Functions
The correspondence between the register specification and the port functions is shown below. P22/TXD pin
Register Bit Name Setting Value PMR1 TXD 0 PCR2 PCR22 0 1 1 Legend: X: Don't care. X Pin Function P22 input pin P22 output pin TXD output pin
P21/RXD pin
Register Bit Name Setting Value SCR3 RE 0 PCR2 PCR21 0 1 1 Legend: X: Don't care. X Pin Function P21 input pin P21 output pin RXD input pin
P20/SCK3 pin
Register Bit Name Setting Value SCR3 CKE1 0 CKE0 0 SMR COM 0 PCR2 PCR20 0 1 0 0 1 Legend: X: Don't care. 0 1 X 1 X X X X X Pin Function P20 input pin P20 output pin SCK3 output pin SCK3 output pin SCK3 input pin
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Section 9 I/O Ports
9.3
Port 5
Port 5 is a general I/O port also functioning as an I2C bus interface I/O pin, an A/D trigger input pin, wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.3. The register setting of the I2C bus interface register has priority for functions of the pins P57/SCL and P56/SDA. Since the output buffer for pins P56 and P57 has the NMOS push-pull structure, it differs from an output buffer with the CMOS structure in the high-level output characteristics (see section 21, Electrical Characteristics).
H8/3694 P57/SCL P56/SDA P55/WKP5/ADTRG
Port 5
H8/3694N
SCL SDA P55/WKP5/ADTRG Port 5 P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0
P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0
Figure 9.3 Port 5 Pin Configuration Port 5 has the following registers. * * * * Port mode register 5 (PMR5) Port control register 5 (PCR5) Port data register 5 (PDR5) Port pull-up control register 5 (PUCR5)
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Section 9 I/O Ports
9.3.1
Port Mode Register 5 (PMR5)
PMR5 switches the functions of pins in port 5.
Bit 7, 6 5 Bit Name WKP5 Initial Value All 0 0 R/W R/W Description Reserved These bits are always read as 0. P55/WKP5/ADTRG Pin Function Switch Selects whether pin P55/WKP5/ADTRG is used as P55 or as WKP5/ADTRG input. 0: General I/O port 1: WKP5/ADTRG input pin 4 WKP4 0 R/W P54/WKP4 Pin Function Switch Selects whether pin P54/WKP4 is used as P54 or as WKP4. 0: General I/O port 1: WKP4 input pin 3 WKP3 0 R/W P53/WKP3 Pin Function Switch Selects whether pin P53/WKP3 is used as P53 or as WKP3. 0: General I/O port 1: WKP3 input pin 2 WKP2 0 R/W P52/WKP2 Pin Function Switch Selects whether pin P52/WKP2 is used as P52 or as WKP2. 0: General I/O port 1: WKP2 input pin 1 WKP1 0 R/W P51/WKP1 Pin Function Switch Selects whether pin P51/WKP1 is used as P51 or as WKP1. 0: General I/O port 1: WKP1 input pin 0 WKP0 0 R/W P50/WKP0 Pin Function Switch Selects whether pin P50/WKP0 is used as P50 or as WKP0. 0: General I/O port 1: WKP0 input pin
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Section 9 I/O Ports
9.3.2
Port Control Register 5 (PCR5)
PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR57 PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When each of the port 5 pins P57 to P50 functions as an general I/O port, setting a PCR5 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Note: The PCR57 and PCR56 bits should not be set to 1 in the H8/3694N.
9.3.3
Port Data Register 5 (PDR5)
PDR5 is a general I/O port data register of port 5.
Bit 7 6 5 4 3 2 1 0 Bit Name P57 P56 P55 P54 P53 P52 P51 P50 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Stores output data for port 5 pins. If PDR5 is read while PCR5 bits are set to 1, the value stored in PDR5 are read. If PDR5 is read while PCR5 bits are cleared to 0, the pin states are read regardless of the value stored in PDR5. Note: The P57 and P56 bits should not be set to 1 in the H8/3694N.
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9.3.4
Port Pull-Up Control Register 5 (PUCR5)
PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports.
Bit 7, 6 5 4 3 2 1 0 Bit Name PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 Initial Value All 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Description Reserved These bits are always read as 0. Only bits for which PCR5 is cleared are valid. The pull-up MOS of the corresponding pins enter the on-state when these bits are set to 1, while they enter the off-state when these bits are cleared to 0.
9.3.5
Pin Functions
The correspondence between the register specification and the port functions is shown below. P57/SCL pin
Register Bit Name Setting Value ICCR1 ICE 0 PCR5 PCR57 0 1 1 Legend: X: Don't care. X Pin Function P57 input pin P57 output pin SCL I/O pin
SCL performs the NMOS open-drain output, that enables a direct bus drive.
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Section 9 I/O Ports
P56/SDA pin
Register Bit Name Setting Value ICCR1 ICE 0 PCR5 PCR56 0 1 1 Legend: X: Don't care. X Pin Function P56 input pin P56 output pin SDA I/O pin
SDA performs the NMOS open-drain output, that enables a direct bus drive. P55/WKP5/ADTRG pin
Register Bit Name Setting Value PMR5 WKP5 0 PCR5 PCR55 0 1 1 Legend: X: Don't care. X Pin Function P55 input pin P55 output pin WKP5/ADTRG input pin
P54/WKP4 pin
Register Bit Name Setting Value PMR5 WKP4 0 PCR5 PCR54 0 1 1 Legend: X: Don't care. X Pin Function P54 input pin P54 output pin WKP4 input pin
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Section 9 I/O Ports
P53/WKP3 pin
Register Bit Name Setting Value PMR5 WKP3 0 PCR5 PCR53 0 1 1 Legend: X: Don't care. X Pin Function P53 input pin P53 output pin WKP3 input pin
P52/WKP2 pin
Register Bit Name Setting Value PMR5 WKP2 0 PCR5 PCR52 0 1 1 Legend: X: Don't care. X Pin Function P52 input pin P52 output pin WKP2 input pin
P51/WKP1 pin
Register Bit Name Setting Value PMR5 WKP1 0 PCR5 PCR51 0 1 1 Legend: X: Don't care. X Pin Function P51 input pin P51 output pin WKP1 input pin
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Section 9 I/O Ports
P50/WKP0 pin
Register Bit Name Setting Value PMR5 WKP0 0 PCR5 PCR50 0 1 1 Legend: X: Don't care. X Pin Function P50 input pin P50 output pin WKP0 input pin
9.4
Port 7
Port 7 is a general I/O port also functioning as a timer V I/O pin. Each pin of the port 7 is shown in figure 9.4. The register setting of TCSRV in timer V has priority for functions of pin P76/TMOV. The pins, P75/TMCIV and P74/TMRIV, are also functioning as timer V input ports that are connected to the timer V regardless of the register setting of port 7.
P76/TMOV Port 7 P75/TMCIV P74/TMRIV
Figure 9.4 Port 7 Pin Configuration Port 7 has the following registers. * Port control register 7 (PCR7) * Port data register 7 (PDR7)
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Section 9 I/O Ports
9.4.1
Port Control Register 7 (PCR7)
PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 7.
Bit 7 6 5 4 3 to 0 Bit Name PCR76 PCR75 PCR74 Initial Value 0 0 0 R/W W W W Description Reserved Setting a PCR7 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Note that the TCSRV setting of the timer V has priority for deciding input/output direction of the P76/TMOV pin. Reserved
9.4.2
Port Data Register 7 (PDR7)
PDR7 is a general I/O port data register of port 7.
Bit 7 6 5 4 Bit Name P76 P75 P74 Initial Value 1 0 0 0 R/W R/W R/W R/W Description Reserved This bit is always read as 1. PDR7 stores output data for port 7 pins. If PDR7 is read while PCR7 bits are set to 1, the value stored in PDR7 is read. If PDR7 is read while PCR7 bits are cleared to 0, the pin states are read regardless of the value stored in PDR7. Reserved These bits are always read as 1.
3 to 0
All 1
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Section 9 I/O Ports
9.4.3
Pin Functions
The correspondence between the register specification and the port functions is shown below. P76/TMOV pin
Register Bit Name Setting Value TCSRV PCR7 Pin Function P76 input pin P76 output pin TMOV output pin
OS3 to OS0 PCR76 0000 0 1 Other than the above values X
Legend: X: Don't care.
P75/TMCIV pin
Register Bit Name Setting Value PCR7 PCR75 0 1 Pin Function P75 input/TMCIV input pin P75 output/TMCIV input pin
P74/TMRIV pin
Register Bit Name Setting Value PCR7 PCR74 0 1 Pin Function P74 input/TMRIV input pin P74 output/TMRIV input pin
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Section 9 I/O Ports
9.5
Port 8
Port 8 is a general I/O port also functioning as a timer W I/O pin. Each pin of the port 8 is shown in figure 9.5. The register setting of the timer W has priority for functions of the pins P84/FTIOD, P83/FTIOC, P82/FTIOB, and P81/FTIOA. P80/FTCI also functions as a timer W input port that is connected to the timer W regardless of the register setting of port 8.
P87 P86 P85 Port 8 P84/FTIOD P83/FTIOC P82/FTIOB P81/FTIOA P80/FTCI
Figure 9.5 Port 8 Pin Configuration Port 8 has the following registers. * Port control register 8 (PCR8) * Port data register 8 (PDR8) 9.5.1 Port Control Register 8 (PCR8)
PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR87 PCR86 PCR85 PCR84 PCR83 PCR82 PCR81 PCR80 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When each of the port 8 pins P87 to P80 functions as an general I/O port, setting a PCR8 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
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Section 9 I/O Ports
9.5.2
Port Data Register 8 (PDR8)
PDR8 is a general I/O port data register of port 8.
Bit 7 6 5 4 3 2 1 0 Bit Name P87 P86 P85 P84 P83 P82 P81 P80 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PDR8 stores output data for port 8 pins. If PDR8 is read while PCR8 bits are set to 1, the value stored in PDR8 is read. If PDR8 is read while PCR8 bits are cleared to 0, the pin states are read regardless of the value stored in PDR8.
9.5.3
Pin Functions
The correspondence between the register specification and the port functions is shown below. P87 pin
Register Bit Name Setting Value PCR8 PCR87 0 1 Pin Function P87 input pin P87 output pin
P86 pin
Register Bit Name Setting Value PCR8 PCR86 0 1 Pin Function P86 input pin P86 output pin
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P85 pin
Register Bit Name Setting Value PCR8 PCR85 0 1 Pin Function P85 input pin P85 output pin
P84/FTIOD pin
Register Bit Name Setting Value TIOR1 IOD2 0 IOD1 0 IOD0 0 PCR8 PCR84 0 1 0 0 1 Legend: X: Don't care. 0 1 X 1 X X X X 0 1 Pin Function P84 input/FTIOD input pin P84 output/FTIOD input pin FTIOD output pin FTIOD output pin P84 input/FTIOD input pin P84 output/FTIOD input pin
P83/FTIOC pin
Register Bit Name Setting Value TIOR1 IOC2 0 IOC1 0 IOC0 0 PCR8 PCR83 0 1 0 0 1 Legend: X: Don't care. 0 1 X 1 X X X X 0 1 Pin Function P83 input/FTIOC input pin P83 output/FTIOC input pin FTIOC output pin FTIOC output pin P83 input/FTIOC input pin P83 output/FTIOC input pin
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Section 9 I/O Ports
P82/FTIOB pin
Register Bit Name Setting Value TIOR0 IOB2 0 IOB1 0 IOB0 0 PCR8 PCR82 0 1 0 0 1 Legend: X: Don't care. 0 1 X 1 X X X X 0 1 Pin Function P82 input/FTIOB input pin P82 output/FTIOB input pin FTIOB output pin FTIOB output pin P82 input/FTIOB input pin P82 output/FTIOB input pin
P81/FTIOA pin
Register Bit Name Setting Value TIOR0 IOA2 0 IOA1 0 IOA0 0 PCR8 PCR81 0 1 0 0 1 Legend: X: Don't care. 0 1 X 1 X X X X 0 1 Pin Function P81 input/FTIOA input pin P81 output/FTIOA input pin FTIOA output pin FTIOA output pin P81 input/FTIOA input pin P81 output/FTIOA input pin
P80/FTCI pin
Register Bit Name Setting Value PCR8 PCR80 0 1 Pin Function P80 input/FTCI input pin P80 output/FTCI input pin
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Section 9 I/O Ports
9.6
Port B
Port B is an input port also functioning as an A/D converter analog input pin. Each pin of the port B is shown in figure 9.6.
PB7/AN7 PB6/AN6 PB5/AN5 Port B PB4/AN4 PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0
Figure 9.6 Port B Pin Configuration Port B has the following register. * Port data register B (PDRB) 9.6.1 Port Data Register B (PDRB)
PDRB is a general input-only port data register of port B.
Bit 7 6 5 4 3 2 1 0 Bit Name PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Initial Value R/W R R R R R R R R Description The input value of each pin is read by reading this register. However, if a port B pin is designated as an analog input channel by ADCSR in A/D converter, 0 is read.
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Section 10 Timer A
Section 10 Timer A
Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768kHz crystal oscillator is connected. Figure 10.1 shows a block diagram of timer A.
10.1
Features
* Timer A can be used as an interval timer or a clock time base. * An interrupt is requested when the counter overflows. * Any of eight clock signals can be output from pin TMOW: 32.768 kHz divided by 32, 16, 8, or 4 (1 kHz, 2 kHz, 4 kHz, 8 kHz), or the system clock divided by 32, 16, 8, or 4. Interval Timer * Choice of eight internal clock sources (/8192, /4096, /2048, /512, /256, /128, /32, 8) Clock Time Base * Choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer A is used as a clock time base (using a 32.768 kHz crystal oscillator).
TIM08A0A_000020020200
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Section 10 Timer A
W
1/4
W/4
PSW
TMA
W/128
TCA
TMOW
/128*
PSS
/256*
/64*
/8*
W/32 W/16 W/8 W/4
/8192, /4096, /2048, /512, /256, /128, /32, /8
IRRTA
[Legend] TMA: Timer mode register A TCA: Timer counter A IRRTA: Timer A overflow interrupt request flag PSW: Prescaler W PSS: Prescaler S Note: * Can be selected only when the prescaler W output (W/128) is used as the TCA input clock.
Figure 10.1 Block Diagram of Timer A
10.2
Input/Output Pins
Table 10.1 shows the timer A input/output pin. Table 10.1 Pin Configuration
Name Clock output Abbreviation I/O TMOW Output Function Output of waveform generated by timer A output circuit
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Internal data bus
W/32 W/16 W/8 W/4
Section 10 Timer A
10.3
Register Descriptions
Timer A has the following registers. * Timer mode register A (TMA) * Timer counter A (TCA) 10.3.1 Timer Mode Register A (TMA)
TMA selects the operating mode, the divided clock output, and the input clock.
Bit 7 6 5 Bit Name TMA7 TMA6 TMA5 Initial Value 0 0 0 R/W R/W R/W R/W Description Clock Output Select 7 to 5 These bits select the clock output at the TMOW pin. 000: /32 001: /16 010: /8 011: /4 100: w/32 101: w/16 110: w/8 111: w/4 For details on clock outputs, see section 10.4.3, Clock Output. 4 3 TMA3 1 0 R/W Reserved This bit is always read as 1. Internal Clock Select 3 This bit selects the operating mode of the timer A. 0: Functions as an interval timer to count the outputs of prescaler S. 1: Functions as a clock-time base to count the outputs of prescaler W.
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Section 10 Timer A
Bit 2 1 0
Bit Name TMA2 TMA1 TMA0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Internal Clock Select 2 to 0 These bits select the clock input to TCA when TMA3 = 0. 000: /8192 001: /4096 010: /2048 011: /512 100: /256 101: /128 110: /32 111: /8 These bits select the overflow period when TMA3 = 1 (when a 32.768 kHz crystal oscillator with is used as W). 000: 1s 001: 0.5 s 010: 0.25 s 011: 0.03125 s 1XX: Both PSW and TCA are reset
Legend: X: Don't care.
10.3.2
Timer Counter A (TCA)
TCA is an 8-bit readable up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in TMA. TCA values can be read by the CPU in active mode, but cannot be read in subactive mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1. TCA is cleared by setting bits TMA3 and TMA2 in TMA to B'11. TCA is initialized to H'00.
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Section 10 Timer A
10.4
10.4.1
Operation
Interval Timer Operation
When bit TMA3 in TMA is cleared to 0, timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting of timer A resume immediately as an interval timer. The clock input to timer A is selected by bits TMA2 to TMA0 in TMA; any of eight internal clock signals output by prescaler S can be selected. After the count value in TCA reaches H'FF, the next clock signal input causes timer A to overflow, setting bit IRRTA to 1 in interrupt Flag Register 1 (IRR1). If IENTA = 1 in interrupt enable register 1 (IENR1), a CPU interrupt is requested. At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as an interval timer that generates an overflow output at intervals of 256 input clock pulses. 10.4.2 Clock Time Base Operation
When bit TMA3 in TMA is set to 1, timer A functions as a clock-timer base by counting clock signals output by prescaler W. When a clock signal is input after the TCA counter value has become H'FF, timer A overflows and IRRTA in IRR1 is set to 1. At that time, an interrupt request is generated to the CPU if IENTA in the interrupt enable register 1 (IENR1) is 1. The overflow period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four periods is available. In clock time base operation (TMA3 = 1), setting bit TMA2 to 1 clears both TCA and prescaler W to H'00. 10.4.3 Clock Output
Setting bit TMOW in port mode register 1 (PMR1) to 1 causes a clock signal to be output at pin TMOW. Eight different clock output signals can be selected by means of bits TMA7 to TMA5 in TMA. The system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A 32.768 kHz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode.
10.5
Usage Note
When the clock time base function is selected as the internal clock of TCA in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. This may result in a maximum error of 1/ (s) in the count cycle.
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Section 10 Timer A
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Section 11 Timer V
Section 11 Timer V
Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Comparematch signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at the TRGV pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. Figure 11.1 shows a block diagram of timer V.
11.1
Features
* Choice of seven clock signals is available. Choice of six internal clock sources (/128, /64, /32, /16, /8, /4) or an external clock. * Counter can be cleared by compare match A or B, or by an external reset signal. If the count stop function is selected, the counter can be halted when cleared. * Timer output is controlled by two independent compare match signals, enabling pulse output with an arbitrary duty cycle, PWM output, and other applications. * Three interrupt sources: compare match A, compare match B, timer overflow * Counting can be initiated by trigger input at the TRGV pin. The rising edge, falling edge, or both edges of the TRGV input can be selected.
TIM08V0A_000120030300
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Section 11 Timer V
TCRV1
TCORB TRGV Trigger control Comparator
Comparator PSS TCORA Clear control
TMRIV
TCRV0 Interrupt request control
TMOV
Output control
TCSRV CMIA CMIB OVI
[Legend] TCORA: TCORB: TCNTV: TCSRV: TCRV0: TCRV1: PSS: CMIA: CMIB: OVI:
Time constant register A Time constant register B Timer counter V Timer control/status register V Timer control register V0 Timer control register V1 Prescaler S Compare-match interrupt A Compare-match interrupt B Overflow interupt
Figure 11.1 Block Diagram of Timer V
11.2
Input/Output Pins
Table 11.1 shows the timer V pin configuration. Table 11.1 Pin Configuration
Name Timer V output Timer V clock input Timer V reset input Trigger input Abbreviation I/O TMOV TMCIV TMRIV TRGV Output Input Input Input Function Timer V waveform output Clock input to TCNTV External input to reset TCNTV Trigger input to initiate counting
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Internal data bus
TMCIV
Clock select
TCNTV
Section 11 Timer V
11.3
Register Descriptions
Time V has the following registers. * * * * * * Timer counter V (TCNTV) Timer constant register A (TCORA) Timer constant register B (TCORB) Timer control register V0 (TCRV0) Timer control/status register V (TCSRV) Timer control register V1 (TCRV1) Timer Counter V (TCNTV)
11.3.1
TCNTV is an 8-bit up-counter. The clock source is selected by bits CKS2 to CKS0 in timer control register V0 (TCRV0). The TCNTV value can be read and written by the CPU at any time. TCNTV can be cleared by an external reset input signal, or by compare match A or B. The clearing signal is selected by bits CCLR1 and CCLR0 in TCRV0. When TCNTV overflows, OVF is set to 1 in timer control/status register V (TCSRV). TCNTV is initialized to H'00. 11.3.2 Time Constant Registers A and B (TCORA, TCORB)
TCORA and TCORB have the same function. TCORA and TCORB are 8-bit read/write registers. TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match, CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested. Note that they must not be compared during the T3 state of a TCORA write cycle. Timer output from the TMOV pin can be controlled by the identifying signal (compare match A) and the settings of bits OS3 to OS0 in TCSRV. TCORA and TCORB are initialized to H'FF.
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Section 11 Timer V
11.3.3
Timer Control Register V0 (TCRV0)
TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV, and controls each interrupt request.
Bit 7 Bit Name CMIEB Initial Value 0 R/W R/W Description Compare Match Interrupt Enable B When this bit is set to 1, interrupt request from the CMFB bit in TCSRV is enabled. 6 CMIEA 0 R/W Compare Match Interrupt Enable A When this bit is set to 1, interrupt request from the CMFA bit in TCSRV is enabled. 5 OVIE 0 R/W Timer Overflow Interrupt Enable When this bit is set to 1, interrupt request from the OVF bit in TCSRV is enabled. 4 3 CCLR1 CCLR0 0 0 R/W R/W Counter Clear 1 and 0 These bits specify the clearing conditions of TCNTV. 00: Clearing is disabled 01: Cleared by compare match A 10: Cleared by compare match B 11: Cleared on the rising edge of the TMRIV pin. The operation of TCNTV after clearing depends on TRGE in TCRV1. 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0 These bits select clock signals to input to TCNTV and the counting condition in combination with ICKS0 in TCRV1. Refer to table 11.2.
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Section 11 Timer V
Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions
TCRV0 Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 TCRV1 Bit 0 ICKS0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 1 Description Clock input prohibited Internal clock: counts on /4, falling edge Internal clock: counts on /8, falling edge Internal clock: counts on /16, falling edge Internal clock: counts on /32, falling edge Internal clock: counts on /64, falling edge Internal clock: counts on /128, falling edge Clock input prohibited External clock: counts on rising edge External clock: counts on falling edge External clock: counts on rising and falling edge
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Section 11 Timer V
11.3.4
Timer Control/Status Register V (TCSRV)
TCSRV indicates the status flag and controls outputs by using a compare match.
Bit 7 Bit Name CMFB Initial Value 0 R/W R/W Description Compare Match Flag B Setting condition: When the TCNTV value matches the TCORB value Clearing condition: After reading CMFB = 1, cleared by writing 0 to CMFB 6 CMFA 0 R/W Compare Match Flag A Setting condition: When the TCNTV value matches the TCORA value Clearing condition: After reading CMFA = 1, cleared by writing 0 to CMFA 5 OVF 0 R/W Timer Overflow Flag Setting condition: When TCNTV overflows from H'FF to H'00 Clearing condition: After reading OVF = 1, cleared by writing 0 to OVF 4 3 2 OS3 OS2 1 0 0 R/W R/W Reserved This bit is always read as 1. Output Select 3 and 2 These bits select an output method for the TMOV pin by the compare match of TCORB and TCNTV. 00: No change 01: 0 output 10: 1 output 11: Output toggles 1 0 OS1 OS0 0 0 R/W R/W Output Select 1 and 0 These bits select an output method for the TMOV pin by the compare match of TCORA and TCNTV. 00: No change 01: 0 output 10: 1 output 11: Output toggles
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Section 11 Timer V
OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two output levels can be controlled independently. After a reset, the timer output is 0 until the first compare match. 11.3.5 Timer Control Register V1 (TCRV1)
TCRV1 selects the edge at the TRGV pin, enables TRGV input, and selects the clock input to TCNTV.
Bit 7 to 5 4 3 Bit Name TVEG1 TVEG0 Initial Value All 1 0 0 R/W R/W R/W Description Reserved These bits are always read as 1. TRGV Input Edge Select These bits select the TRGV input edge. 00: TRGV trigger input is prohibited 01: Rising edge is selected 10: Falling edge is selected 11: Rising and falling edges are both selected 2 TRGE 0 R/W TCNT starts counting up by the input of the edge which is selected by TVEG1 and TVEG0. 0: Disables starting counting-up TCNTV by the input of the TRGV pin and halting counting-up TCNTV when TCNTV is cleared by a compare match. 1: Enables starting counting-up TCNTV by the input of the TRGV pin and halting counting-up TCNTV when TCNTV is cleared by a compare match. 1 0 ICKS0 1 0 R/W Reserved This bit is always read as 1. Internal Clock Select 0 This bit selects clock signals to input to TCNTV in combination with CKS2 to CKS0 in TCRV0. Refer to table 11.2.
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Section 11 Timer V
11.4
11.4.1
Operation
Timer V Operation
1. According to table 11.2, six internal/external clock signals output by prescaler S can be selected as the timer V operating clock signals. When the operating clock signal is selected, TCNTV starts counting-up. Figure 11.2 shows the count timing with an internal clock signal selected, and figure 11.3 shows the count timing with both edges of an external clock signal selected. 2. When TCNTV overflows (changes from H'FF to H'00), the overflow flag (OVF) in TCRV0 will be set. The timing at this time is shown in figure 11.4. An interrupt request is sent to the CPU when OVIE in TCRV0 is 1. 3. TCNTV is constantly compared with TCORA and TCORB. Compare match flag A or B (CMFA or CMFB) is set to 1 when TCNTV matches TCORA or TCORB, respectively. The compare-match signal is generated in the last state in which the values match. Figure 11.5 shows the timing. An interrupt request is generated for the CPU when CMIEA or CMIEB in TCRV0 is 1. 4. When a compare match A or B is generated, the TMOV responds with the output value selected by bits OS3 to OS0 in TCSRV. Figure 11.6 shows the timing when the output is toggled by compare match A. 5. When CCLR1 or CCLR0 in TCRV0 is 01 or 10, TCNTV can be cleared by the corresponding compare match. Figure 11.7 shows the timing. 6. When CCLR1 or CCLR0 in TCRV0 is 11, TCNTV can be cleared by the rising edge of the input of TMRIV pin. A TMRIV input pulse-width of at least 1.5 system clocks is necessary. Figure 11.8 shows the timing. 7. When a counter-clearing source is generated with TRGE in TCRV1 set to 1, the counting-up is halted as soon as TCNTV is cleared. TCNTV resumes counting-up when the edge selected by TVEG1 or TVEG0 in TCRV1 is input from the TGRV pin.
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Section 11 Timer V
Internal clock
TCNTV input clock
TCNTV
N-1
N
N+1
Figure 11.2 Increment Timing with Internal Clock
TMCIV (External clock input pin) TCNTV input clock
TCNTV
N-1
N
N+1
Figure 11.3 Increment Timing with External Clock
TCNTV H'FF H'00
Overflow signal
OVF
Figure 11.4 OVF Set Timing
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Section 11 Timer V
TCNTV N N+1
TCORA or TCORB Compare match signal CMFA or CMFB
N
Figure 11.5 CMFA and CMFB Set Timing
Compare match A signal
Timer V output pin
Figure 11.6 TMOV Output Timing
Compare match A signal
TCNTV
N
H'00
Figure 11.7 Clear Timing by Compare Match
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Section 11 Timer V
TMRIV(External counter reset input pin ) TCNTV reset signal TCNTV N-1 N
H'00
Figure 11.8 Clear Timing by TMRIV Input
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Section 11 Timer V
11.5
11.5.1
Timer V Application Examples
Pulse Output with Arbitrary Duty Cycle
Figure 11.9 shows an example of output of pulses with an arbitrary duty cycle. 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORA. 2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. 3. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source. 4. With these settings, a waveform is output without further software intervention, with a period determined by TCORA and a pulse width determined by TCORB.
TCNTV value H'FF Counter cleared TCORA TCORB H'00
TMOV
Time
Figure 11.9 Pulse Output Example
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Section 11 Timer V
11.5.2
Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input
The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 11.10. To set up this output: 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORB. 2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. 3. Set bits TVEG1 and TVEG0 in TCRV1 and set TRGE to select the falling edge of the TRGV input. 4. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source. 5. After these settings, a pulse waveform will be output without further software intervention, with a delay determined by TCORA from the TRGV input, and a pulse width determined by (TCORB - TCORA).
TCNTV value H'FF Counter cleared TCORB TCORA H'00 TRGV Time
TMOV
Compare match A Compare match A
Compare match B clears TCNTV and halts count-up
Compare match B clears TCNTV and halts count-up
Figure 11.10 Example of Pulse Output Synchronized to TRGV Input
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Section 11 Timer V
11.6
Usage Notes
The following types of contention or operation can occur in timer V operation. 1. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 11.11, clearing takes precedence and the write to the counter is not carried out. If counting-up is generated in the T3 state of a TCNTV write cycle, writing takes precedence. If a compare match is generated in the T3 state of a TCORA or TCORB write cycle, the write to TCORA or TCORB takes precedence and the compare match signal is inhibited. Figure 11.12 shows the timing. If compare matches A and B occur simultaneously, any conflict between the output selections for compare match A and compare match B is resolved by the following priority: toggle output > output 1 > output 0. Depending on the timing, TCNTV may be incremented by a switch between different internal clock sources. When TCNTV is internally clocked, an increment pulse is generated from the falling edge of an internal clock signal, that is divided system clock (). Therefore, as shown in figure 11.3 the switch is from a high clock signal to a low clock signal, the switchover is seen as a falling edge, causing TCNTV to increment. TCNTV can also be incremented by a switch between internal and external clocks.
TCNTV write cycle by CPU T1 T2 T3
2.
3.
4.
Address
TCNTV address
Internal write signal
Counter clear signal
TCNTV
N
H'00
Figure 11.11 Contention between TCNTV Write and Clear
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Section 11 Timer V
TCORA write cycle by CPU T1 T2 T3
Address
TCORA address
Internal write signal
TCNTV
N
N+1
TCORA
N
M TCORA write data
Compare match signal Inhibited
Figure 11.12 Contention between TCORA Write and Compare Match
Clock before switching
Clock after switching
Count clock
TCNTV
N
N+1
N+2
Write to CKS1 and CKS0
Figure 11.13 Internal Clock Switching and TCNTV Operation
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Section 11 Timer V
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Section 12 Timer W
Section 12 Timer W
The timer W has a 16-bit timer having output compare and input capture functions. The timer W can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. Thus, it can be applied to various systems.
12.1
Features
* Selection of five counter clock sources: four internal clocks (, /2, /4, and /8) and an external clock (external events can be counted) * Capability to process up to four pulse outputs or four pulse inputs * Four general registers: Independently assignable output compare or input capture functions Usable as two pairs of registers; one register of each pair operates as a buffer for the output compare or input capture register * Four selectable operating modes : Waveform output by compare match Selection of 0 output, 1 output, or toggle output Input capture function Rising edge, falling edge, or both edges Counter clearing function Counters can be cleared by compare match PWM mode Up to three-phase PWM output can be provided with desired duty ratio. * Any initial timer output value can be set * Five interrupt sources Four compare match/input capture interrupts and an overflow interrupt. Table 12.1 summarizes the timer W functions, and figure 12.1 shows a block diagram of the timer W.
TIM08W0A_000020020200
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Section 12 Timer W
Table 12.1 Timer W Functions
Input/Output Pins Item Count clock General registers (output compare/input capture registers) Counter clearing function Counter FTIOA FTIOB FTIOC FTIOD Internal clocks: , /2, /4, /8 External clock: FTCI Period GRA specified in GRA GRA compare match -- -- 0 1 Toggle Input capture function PWM mode Interrupt sources -- -- -- -- -- Overflow GRA compare match Yes Yes Yes Yes Yes Yes -- Compare match/input capture GRB GRC (buffer register for GRA in buffer mode) -- GRD (buffer register for GRB in buffer mode) --
--
Initial output value setting function Buffer function Compare match output
Yes Yes Yes Yes Yes Yes Yes Compare match/input capture
Yes -- Yes Yes Yes Yes Yes Compare match/input capture
Yes -- Yes Yes Yes Yes Yes Compare match/input capture
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Section 12 Timer W
Internal clock: /2 /4 /8 External clock: FTCI
FTIOA Clock selector Control logic Comparator FTIOB FTIOC FTIOD IRRTW
TIERW
TMRW
TCRW
TSRW
TCNT
TIOR
GRC
GRD
GRA
GRB
[Legend] TMRW: TCRW: TIERW: TSRW: TIOR: TCNT: GRA: GRB: GRC: GRD: IRRTW:
Timer mode register W (8 bits) Timer control register W (8 bits) Timer interrupt enable register W (8 bits) Timer status register W (8 bits) Timer I/O control register (8 bits) Timer counter (16 bits) General register A (input capture/output compare register: 16 bits) General register B (input capture/output compare register: 16 bits) General register C (input capture/output compare register: 16 bits) General register D (input capture/output compare register: 16 bits) Timer W interrupt request
Figure 12.1 Timer W Block Diagram
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Bus interface
Internal data bus
Section 12 Timer W
12.2
Input/Output Pins
Table 12.2 summarizes the timer W pins. Table 12.2 Pin Configuration
Name External clock input Input capture/output compare A Input capture/output compare B Input capture/output compare C Input capture/output compare D Abbreviation FTCI FTIOA FTIOB Input/Output Input Input/output Input/output Function External clock input pin Output pin for GRA output compare or input pin for GRA input capture Output pin for GRB output compare, input pin for GRB input capture, or PWM output pin in PWM mode Output pin for GRC output compare, input pin for GRC input capture, or PWM output pin in PWM mode Output pin for GRD output compare, input pin for GRD input capture, or PWM output pin in PWM mode
FTIOC
Input/output
FTIOD
Input/output
12.3
Register Descriptions
The timer W has the following registers. * * * * * * * * * * * Timer mode register W (TMRW) Timer control register W (TCRW) Timer interrupt enable register W (TIERW) Timer status register W (TSRW) Timer I/O control register 0 (TIOR0) Timer I/O control register 1 (TIOR1) Timer counter (TCNT) General register A (GRA) General register B (GRB) General register C (GRC) General register D (GRD)
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Section 12 Timer W
12.3.1
Timer Mode Register W (TMRW)
TMRW selects the general register functions and the timer output mode.
Bit 7 Bit Name CTS Initial Value 0 R/W R/W Description Counter Start The counter operation is halted when this bit is 0, while it can be performed when this bit is 1. 6 5 BUFEB 1 0 R/W Reserved This bit is always read as 1. Buffer Operation B Selects the GRD function. 0: GRD operates as an input capture/output compare register 1: GRD operates as the buffer register for GRB 4 BUFEA 0 R/W Buffer Operation A Selects the GRC function. 0: GRC operates as an input capture/output compare register 1: GRC operates as the buffer register for GRA 3 2 PWMD 1 0 R/W Reserved This bit is always read as 1. PWM Mode D Selects the output mode of the FTIOD pin. 0: FTIOD operates normally (output compare output) 1: PWM output 1 PWMC 0 R/W PWM Mode C Selects the output mode of the FTIOC pin. 0: FTIOC operates normally (output compare output) 1: PWM output 0 PWMB 0 R/W PWM Mode B Selects the output mode of the FTIOB pin. 0: FTIOB operates normally (output compare output) 1: PWM output
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Section 12 Timer W
12.3.2
Timer Control Register W (TCRW)
TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer output levels.
Bit 7 Bit Name CCLR Initial Value 0 R/W R/W Description Counter Clear The TCNT value is cleared by compare match A when this bit is 1. When it is 0, TCNT operates as a freerunning counter. 6 5 4 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0 Select the TCNT clock source. 000: Internal clock: counts on 001: Internal clock: counts on /2 010: Internal clock: counts on /4 011: Internal clock: counts on /8 1XX: Counts on rising edges of the external event (FTCI) When the internal clock source () is selected, subclock sources are counted in subactive and subsleep modes. 3 TOD 0 R/W Timer Output Level Setting D Sets the output value of the FTIOD pin until the first compare match D is generated. 0: Output value is 0* 1: Output value is 1* 2 TOC 0 R/W Timer Output Level Setting C Sets the output value of the FTIOC pin until the first compare match C is generated. 0: Output value is 0* 1: Output value is 1* 1 TOB 0 R/W Timer Output Level Setting B Sets the output value of the FTIOB pin until the first compare match B is generated. 0: Output value is 0* 1: Output value is 1*
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Section 12 Timer W
Bit 0
Bit Name TOA
Initial Value 0
R/W R/W
Description Timer Output Level Setting A Sets the output value of the FTIOA pin until the first compare match A is generated. 0: Output value is 0* 1: Output value is 1*
Legend: Note: *
X: Don't care. The change of the setting is immediately reflected in the output value.
12.3.3
Timer Interrupt Enable Register W (TIERW)
TIERW controls the timer W interrupt request.
Bit 7 Bit Name OVIE Initial Value 0 R/W R/W Description Timer Overflow Interrupt Enable When this bit is set to 1, FOVI interrupt requested by OVF flag in TSRW is enabled. 6 to 4 3 IMIED All 1 0 R/W Reserved These bits are always read as 1. Input Capture/Compare Match Interrupt Enable D When this bit is set to 1, IMID interrupt requested by IMFD flag in TSRW is enabled. 2 IMIEC 0 R/W Input Capture/Compare Match Interrupt Enable C When this bit is set to 1, IMIC interrupt requested by IMFC flag in TSRW is enabled. 1 IMIEB 0 R/W Input Capture/Compare Match Interrupt Enable B When this bit is set to 1, IMIB interrupt requested by IMFB flag in TSRW is enabled. 0 IMIEA 0 R/W Input Capture/Compare Match Interrupt Enable A When this bit is set to 1, IMIA interrupt requested by IMFA flag in TSRW is enabled.
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Section 12 Timer W
12.3.4
Timer Status Register W (TSRW)
TSRW shows the status of interrupt requests.
Bit 7 Bit Name OVF Initial Value 0 R/W R/W Description Timer Overflow Flag [Setting condition] When TCNT overflows from H'FFFF to H'0000 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 6 to 4 3 IMFD All 1 0 R/W Reserved These bits are always read as 1. Input Capture/Compare Match Flag D [Setting conditions] * * TCNT = GRD when GRD functions as an output compare register The TCNT value is transferred to GRD by an input capture signal when GRD functions as an input capture register
[Clearing condition] Read IMFD when IMFD = 1, then write 0 in IMFD 2 IMFC 0 R/W Input Capture/Compare Match Flag C [Setting conditions] * * TCNT = GRC when GRC functions as an output compare register The TCNT value is transferred to GRC by an input capture signal when GRC functions as an input capture register
[Clearing condition] Read IMFC when IMFC = 1, then write 0 in IMFC
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Section 12 Timer W
Bit 1
Bit Name IMFB
Initial Value 0
R/W R/W
Description Input Capture/Compare Match Flag B [Setting conditions] * * TCNT = GRB when GRB functions as an output compare register The TCNT value is transferred to GRB by an input capture signal when GRB functions as an input capture register
[Clearing condition] Read IMFB when IMFB = 1, then write 0 in IMFB 0 IMFA 0 R/W Input Capture/Compare Match Flag A [Setting conditions] * * TCNT = GRA when GRA functions as an output compare register The TCNT value is transferred to GRA by an input capture signal when GRA functions as an input capture register
[Clearing condition] Read IMFA when IMFA = 1, then write 0 in IMFA
12.3.5
Timer I/O Control Register 0 (TIOR0)
TIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and FTIOB pins.
Bit 7 6 Bit Name IOB2 Initial Value 1 0 R/W R/W Description Reserved This bit is always read as 1. I/O Control B2 Selects the GRB function. 0: GRB functions as an output compare register 1: GRB functions as an input capture register
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Section 12 Timer W
Bit 5 4
Bit Name IOB1 IOB0
Initial Value 0 0
R/W R/W R/W
Description I/O Control B1 and B0 When IOB2 = 0, 00: No output at compare match 01: 0 output to the FTIOB pin at GRB compare match 10: 1 output to the FTIOB pin at GRB compare match 11: Output toggles to the FTIOB pin at GRB compare match When IOB2 = 1, 00: Input capture at rising edge at the FTIOB pin 01: Input capture at falling edge at the FTIOB pin 1X: Input capture at rising and falling edges of the FTIOB pin
3 2
IOA2
1 0
R/W
Reserved This bit is always read as 1. I/O Control A2 Selects the GRA function. 0: GRA functions as an output compare register 1: GRA functions as an input capture register
1 0
IOA1 IOA0
0 0
R/W R/W
I/O Control A1 and A0 When IOA2 = 0, 00: No output at compare match 01: 0 output to the FTIOA pin at GRA compare match 10: 1 output to the FTIOA pin at GRA compare match 11: Output toggles to the FTIOA pin at GRA compare match When IOA2 = 1, 00: Input capture at rising edge of the FTIOA pin 01: Input capture at falling edge of the FTIOA pin 1X: Input capture at rising and falling edges of the FTIOA pin
Legend: X: Don't care.
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Section 12 Timer W
12.3.6
Timer I/O Control Register 1 (TIOR1)
TIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and FTIOD pins.
Bit 7 6 Bit Name IOD2 Initial Value 1 0 R/W R/W Description Reserved This bit is always read as 1. I/O Control D2 Selects the GRD function. 0: GRD functions as an output compare register 1: GRD functions as an input capture register 5 4 IOD1 IOD0 0 0 R/W R/W I/O Control D1 and D0 When IOD2 = 0, 00: No output at compare match 01: 0 output to the FTIOD pin at GRD compare match 10: 1 output to the FTIOD pin at GRD compare match 11: Output toggles to the FTIOD pin at GRD compare match When IOD2 = 1, 00: Input capture at rising edge at the FTIOD pin 01: Input capture at falling edge at the FTIOD pin 1X: Input capture at rising and falling edges at the FTIOD pin 3 2 IOC2 1 0 R/W Reserved This bit is always read as 1. I/O Control C2 Selects the GRC function. 0: GRC functions as an output compare register 1: GRC functions as an input capture register
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Section 12 Timer W
Bit 1 0
Bit Name IOC1 IOC0
Initial Value 0 0
R/W R/W R/W
Description I/O Control C1 and C0 When IOC2 = 0, 00: No output at compare match 01: 0 output to the FTIOC pin at GRC compare match 10: 1 output to the FTIOC pin at GRC compare match 11: Output toggles to the FTIOC pin at GRC compare match When IOC2 = 1, 00: Input capture to GRC at rising edge of the FTIOC pin 01: Input capture to GRC at falling edge of the FTIOC pin 1X: Input capture to GRC at rising and falling edges of the FTIOC pin
Legend: X: Don't care.
12.3.7
Timer Counter (TCNT)
TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA by setting the CCLR in TCRW to 1. When TCNT overflows (changes from H'FFFF to H'0000), the OVF flag in TSRW is set to 1. If OVIE in TIERW is set to 1 at this time, an interrupt request is generated. TCNT must always be read or written in 16-bit units; 8-bit access is not allowed. TCNT is initialized to H'0000 by a reset. 12.3.8 General Registers A to D (GRA to GRD)
Each general register is a 16-bit readable/writable register that can function as either an outputcompare register or an input-capture register. The function is selected by settings in TIOR0 and TIOR1. When a general register is used as an input-compare register, its value is constantly compared with the TCNT value. When the two values match (a compare match), the corresponding flag (IMFA, IMFB, IMFC, or IMFD) in TSRW is set to 1. An interrupt request is generated at this time, when IMIEA, IMIEB, IMIEC, or IMIED is set to 1. Compare match output can be selected in TIOR. When a general register is used as an input-capture register, an external input-capture signal is detected and the current TCNT value is stored in the general register. The corresponding flag (IMFA, IMFB, IMFC, or IMFD) in TSRW is set to 1. If the corresponding interrupt-enable bit
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Section 12 Timer W
(IMIEA, IMIEB, IMIEC, or IMIED) in TSRW is set to 1 at this time, an interrupt request is generated. The edge of the input-capture signal is selected in TIOR. GRC and GRD can be used as buffer registers of GRA and GRB, respectively, by setting BUFEA and BUFEB in TMRW. For example, when GRA is set as an output-compare register and GRC is set as the buffer register for GRA, the value in the buffer register GRC is sent to GRA whenever compare match A is generated. When GRA is set as an input-capture register and GRC is set as the buffer register for GRA, the value in TCNT is transferred to GRA and the value in the buffer register GRC is transferred to GRA whenever an input capture is generated. GRA to GRD must be written or read in 16-bit units; 8-bit access is not allowed. GRA to GRD are initialized to H'FFFF by a reset.
12.4
Operation
The timer W has the following operating modes. * Normal Operation * PWM Operation 12.4.1 Normal Operation
TCNT performs free-running or periodic counting operations. After a reset, TCNT is set as a freerunning counter. When the CTS bit in TMRW is set to 1, TCNT starts incrementing the count. When the count overflows from H'FFFF to H'0000, the OVF flag in TSRW is set to 1. If the OVIE in TIERW is set to 1, an interrupt request is generated. Figure 12.2 shows free-running counting.
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Section 12 Timer W
TCNT value H'FFFF
H'0000 CTS bit
Time
Flag cleared by software
OVF
Figure 12.2 Free-Running Counter Operation Periodic counting operation can be performed when GRA is set as an output compare register and bit CCLR in TCRW is set to 1. When the count matches GRA, TCNT is cleared to H'0000, the IMFA flag in TSRW is set to 1. If the corresponding IMIEA bit in TIERW is set to 1, an interrupt request is generated. TCNT continues counting from H'0000. Figure 12.3 shows periodic counting.
TCNT value GRA
H'0000 CTS bit
Flag cleared by software
Time
IMFA
Figure 12.3 Periodic Counter Operation By setting a general register as an output compare register, compare match A, B, C, or D can cause the output at the FTIOA, FTIOB, FTIOC, or FTIOD pin to output 0, output 1, or toggle. Figure 12.4 shows an example of 0 and 1 output when TCNT operates as a free-running counter, 1 output is selected for compare match A, and 0 output is selected for compare match B. When signal is already at the selected output level, the signal level does not change at compare match.
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Section 12 Timer W
TCNT value H'FFFF GRA GRB H'0000 FTIOA FTIOB No change No change Time No change No change
Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1) Figure 12.5 shows an example of toggle output when TCNT operates as a free-running counter, and toggle output is selected for both compare match A and B.
TCNT value H'FFFF
GRA GRB
H'0000 FTIOA FTIOB
Time Toggle output Toggle output
Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1) Figure 12.6 shows another example of toggle output when TCNT operates as a periodic counter, cleared by compare match A. Toggle output is selected for both compare match A and B.
TCNT value
Counter cleared by compare match with GRA
H'FFFF
GRA GRB
H'0000 FTIOA FTIOB
Time Toggle output
Toggle output
Figure 12.6 Toggle Output Example (TOA = 0, TOB = 1)
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Section 12 Timer W
The TCNT value can be captured into a general register (GRA, GRB, GRC, or GRD) when a signal level changes at an input-capture pin (FTIOA, FTIOB, FTIOC, or FTIOD). Capture can take place on the rising edge, falling edge, or both edges. By using the input-capture function, the pulse width and periods can be measured. Figure 12.7 shows an example of input capture when both edges of FTIOA and the falling edge of FTIOB are selected as capture edges. TCNT operates as a free-running counter.
TCNT value
H'FFFF
H'F000
H'AA55 H'55AA
H'1000 H'0000
Time
FTIOA
GRA
H'1000
H'F000
H'55AA
FTIOB
GRB
H'AA55
Figure 12.7 Input Capture Operating Example Figure 12.8 shows an example of buffer operation when the GRA is set as an input-capture register and GRC is set as the buffer register for GRA. TCNT operates as a free-running counter, and FTIOA captures both rising and falling edge of the input signal. Due to the buffer operation, the GRA value is transferred to GRC by input-capture A and the TCNT value is stored in GRA.
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Section 12 Timer W
TCNT value
H'FFFF
H'DA91
H'5480
H'0245 H'0000
FTIOA
Time
GRA
H'0245
H'5480
H'DA91
GRC
H'0245
H'5480
Figure 12.8 Buffer Operation Example (Input Capture) 12.4.2 PWM Operation
In PWM mode, PWM waveforms are generated by using GRA as the period register and GRB, GRC, and GRD as duty registers. PWM waveforms are output from the FTIOB, FTIOC, and FTIOD pins. Up to three-phase PWM waveforms can be output. In PWM mode, a general register functions as an output compare register automatically. The output level of each pin depends on the corresponding timer output level set bit (TOB, TOC, and TOD) in TCRW. When TOB is 1, the FTIOB output goes to 1 at compare match A and to 0 at compare match B. When TOB is 0, the FTIOB output goes to 0 at compare match A and to 1 at compare match B. Thus the compare match output level settings in TIOR0 and TIOR1 are ignored for the output pin set to PWM mode. If the same value is set in the cycle register and the duty register, the output does not change when a compare match occurs. Figure 12.9 shows an example of operation in PWM mode. The output signals go to 1 and TCNT is cleared at compare match A, and the output signals go to 0 at compare match B, C, and D (TOB, TOC, and TOD = 1: initial output values are set to 1).
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Section 12 Timer W
TCNT value GRA GRB GRC
GRD
Counter cleared by compare match A
H'0000 FTIOB FTIOC
Time
FTIOD
Figure 12.9 PWM Mode Example (1) Figure 12.10 shows another example of operation in PWM mode. The output signals go to 0 and TCNT is cleared at compare match A, and the output signals go to 1 at compare match B, C, and D (TOB, TOC, and TOD = 0: initial output values are set to 1).
TCNT value GRA GRB GRC
GRD
Counter cleared by compare match A
H'0000 FTIOB FTIOC
Time
FTIOD
Figure 12.10 PWM Mode Example (2)
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Section 12 Timer W
Figure 12.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB outputs 1 at compare match B and 0 at compare match A. Due to the buffer operation, the FTIOB output level changes and the value of buffer register GRD is transferred to GRB whenever compare match B occurs. This procedure is repeated every time compare match B occurs.
TCNT value GRA
H'0200
H'0450
H'0520
GRB
H'0000 GRD
H'0200
H'0450
Time
H'0520
GRB
H'0200
H'0450
H'0520
FTIOB
Figure 12.11 Buffer Operation Example (Output Compare) Figures 12.12 and 12.13 show examples of the output of PWM waveforms with duty cycles of 0% and 100%.
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Section 12 Timer W
TCNT value GRA
Write to GRB
GRB H'0000 Duty 0%
Write to GRB Time
FTIOB
TCNT value Write to GRB GRA
Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB Write to GRB
GRB H'0000 Duty 100% Time
FTIOB
TCNT value Write to GRB GRA
Output does not change when cycle register and duty register compare matches occur simultaneously.
Write to GRB Write to GRB Time Duty 100% Duty 0%
GRB H'0000
FTIOB
Figure 12.12 PWM Mode Example (TOB, TOC, and TOD = 0: initial output values are set to 0)
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Section 12 Timer W
TCNT value GRA
Write to GRB
GRB
Write to GRB
H'0000
Duty 100%
Time
FTIOB
TCNT value
Write to GRB
Output does not change when cycle register and duty register compare matches occur simultaneously.
GRA
Write to GRB
Write to GRB
GRB
H'0000
Duty 0%
Time
FTIOB
TCNT value
Write to GRB
Output does not change when cycle register and duty register compare matches occur simultaneously.
GRA
Write to GRB Write to GRB
GRB
H'0000
Duty 0%
Duty 100%
Time
FTIOB
Figure 12.13 PWM Mode Example (TOB, TOC, and TOD = 1: initial output values are set to 1)
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Section 12 Timer W
12.5
12.5.1
Operation Timing
TCNT Count Timing
Figure 12.14 shows the TCNT count timing when the internal clock source is selected. Figure 12.15 shows the timing when the external clock source is selected. The pulse width of the external clock signal must be at least two system clock () cycles; shorter pulses will not be counted correctly.
Internal clock TCNT input clock TCNT
N
Rising edge
N+1
N+2
Figure 12.14 Count Timing for Internal Clock Source
External clock TCNT input clock TCNT N N+1
N+2
Rising edge
Rising edge
Figure 12.15 Count Timing for External Clock Source 12.5.2 Output Compare Output Timing
The compare match signal is generated in the last state in which TCNT and GR match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD). When TCNT matches GR, the compare match signal is generated only after the next counter clock pulse is input.
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Section 12 Timer W
Figure 12.16 shows the output compare timing.
TCNT input clock TCNT
N N+1
GRA to GRD Compare match signal FTIOA to FTIOD
N
Figure 12.16 Output Compare Output Timing 12.5.3 Input Capture Timing
Input capture on the rising edge, falling edge, or both edges can be selected through settings in TIOR0 and TIOR1. Figure 12.17 shows the timing when the falling edge is selected. The pulse width of the input capture signal must be at least two system clock () cycles; shorter pulses will not be detected correctly.
Input capture input Input capture signal TCNT GRA to GRD
N-1
N
N+1
N+2
N
Figure 12.17 Input Capture Input Signal Timing
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Section 12 Timer W
12.5.4
Timing of Counter Clearing by Compare Match
Figure 12.18 shows the timing when the counter is cleared by compare match A. When the GRA value is N, the counter counts from 0 to N, and its cycle is N + 1.
Compare match signal
TCNT
N
H'0000
GRA
N
Figure 12.18 Timing of Counter Clearing by Compare Match 12.5.5 Buffer Operation Timing
Figures 12.19 and 12.20 show the buffer operation timing.
Compare match signal TCNT N N+1
GRC, GRD
M
GRA, GRB
M
Figure 12.19 Buffer Operation Timing (Compare Match)
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Section 12 Timer W
Input capture signal TCNT
N
N+1
GRA, GRB
M
N
N+1
GRC, GRD
M
N
Figure 12.20 Buffer Operation Timing (Input Capture) 12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match
If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general register. The compare match signal is generated in the last state in which the values match (when TCNT is updated from the matching count to the next count). Therefore, when TCNT matches a general register, the compare match signal is generated only after the next TCNT clock pulse is input. Figure 12.21 shows the timing of the IMFA to IMFD flag setting at compare match.
TCNT input clock TCNT N N+1
GRA to GRD
Compare match signal
N
IMFA to IMFD
IRRTW
Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match
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Section 12 Timer W
12.5.7
Timing of IMFA to IMFD Setting at Input Capture
If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure 12.22 shows the timing of the IMFA to IMFD flag setting at input capture.
Input capture signal TCNT N
GRA to GRD
N
IMFA to IMFD
IRRTW
Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture 12.5.8 Timing of Status Flag Clearing
When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. Figure 12.23 shows the status flag clearing timing.
TSRW write cycle T1 T2
Address
TSRW address
Write signal
IMFA to IMFD
IRRTW
Figure 12.23 Timing of Status Flag Clearing by CPU
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Section 12 Timer W
12.6
Usage Notes
The following types of contention or operation can occur in timer W operation. 1. The pulse width of the input clock signal and the input capture signal must be at least two system clock () cycles; shorter pulses will not be detected correctly. 2. Writing to registers is performed in the T2 state of a TCNT write cycle. If counter clear signal occurs in the T2 state of a TCNT write cycle, clearing of the counter takes priority and the write is not performed, as shown in figure 12.24. If counting-up is generated in the TCNT write cycle to contend with the TCNT counting-up, writing takes precedence. 3. Depending on the timing, TCNT may be incremented by a switch between different internal clock sources. When TCNT is internally clocked, an increment pulse is generated from the rising edge of an internal clock signal, that is divided system clock (). Therefore, as shown in figure 12.25 the switch is from a low clock signal to a high clock signal, the switchover is seen as a rising edge, causing TCNT to increment. 4. If timer W enters module standby mode while an interrupt request is generated, the interrupt request cannot be cleared. Before entering module standby mode, disable interrupt requests.
TCNT write cycle T2 T1
Address
TCNT address
Write signal Counter clear signal
TCNT
N
H'0000
Figure 12.24 Contention between TCNT Write and Clear
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Section 12 Timer W
Previous clock New clock
Count clock
TCNT
N
N+1
N+2
N+3
The change in signal level at clock switching is assumed to be a rising edge, and TCNT increments the count.
Figure 12.25 Internal Clock Switching and TCNT Operation
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Section 12 Timer W
5. The TOA to TOD bits in TCRW decide the value of the FTIO pin, which is output until the first compare match occurs. Once a compare match occurs and this compare match changes the values of FTIOA to FTIOD output, the values of the FTIOA to FTIOD pin output and the values read from the TOA to TOD bits may differ. Moreover, when the writing to TCRW and the generation of the compare match A to D occur at the same timing, the writing to TCRW has the priority. Thus, output change due to the compare match is not reflected to the FTIOA to FTIOD pins. Therefore, when bit manipulation instruction is used to write to TCRW, the values of the FTIOA to FTIOD pin output may result in an unexpected result. When TCRW is to be written to while compare match is operating, stop the counter once before accessing to TCRW, read the port 8 state to reflect the values of FTIOA to FTIOD output, to TOA to TOD, and then restart the counter. Figure 12.26 shows an example when the compare match and the bit manipulation instruction to TCRW occur at the same timing.
TCRW has been set to H'06. Compare match B and compare match C are used. The FTIOB pin is in the 1 output state, and is set to the toggle output or the 0 output by compare match B. When BCLR#2, @TCRW is executed to clear the TOC bit (the FTIOC signal is low) and compare match B occurs at the same timing as shown below, the H'02 writing to TCRW has priority and compare match B does not drive the FTIOB signal low; the FTIOB signal remains high. Bit TCRW Set value 7 CCLR 0 6 CKS2 0 5 CKS1 0 4 CKS0 0 3 TOD 0 2 TOC 1 1 TOB 1 0 TOA 0
BCLR#2, @TCRW (1) TCRW read operation: Read H'06 (2) Modify operation: Modify H'06 to H'02 (3) Write operation to TCRW: Write H'02
TCRW write signal
Compare match signal B
FTIOB pin Expected output Remains high because the 1 writing to TOB has priority
Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW Occur at the Same Timing
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Section 12 Timer W
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Section 13 Watchdog Timer
Section 13 Watchdog Timer
The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. The block diagram of the watchdog timer is shown in figure 13.1.
Internal oscillator
CLK
TCSRWD
PSS
TCWD
TMWD
[Legend] TCSRWD: TCWD: PSS: TMWD:
Timer control/status register WD Timer counter WD Prescaler S Timer mode register WD
Internal reset signal
Figure 13.1 Block Diagram of Watchdog Timer
13.1
Features
* Selectable from nine counter input clocks. Eight clock sources (/64, /128, /256, /512, /1024, /2048, /4096, and /8192) or the internal oscillator can be selected as the timer-counter clock. When the internal oscillator is selected, it can operate as the watchdog timer in any operating mode. * Reset signal generated on counter overflow An overflow period of 1 to 256 times the selected clock can be set.
WDT0110A_000020020200
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Internal data bus
Section 13 Watchdog Timer
13.2
Register Descriptions
The watchdog timer has the following registers. * Timer control/status register WD (TCSRWD) * Timer counter WD (TCWD) * Timer mode register WD (TMWD) 13.2.1 Timer Control/Status Register WD (TCSRWD)
TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the watchdog timer operation and indicates the operating state. TCSRWD must be rewritten by using the MOV instruction. The bit manipulation instruction cannot be used to change the setting value.
Bit 7 Bit Name B6WI Initial Value 1 R/W R/W Description Bit 6 Write Inhibit The TCWE bit can be written only when the write value of the B6WI bit is 0. This bit is always read as 1. 6 TCWE 0 R/W Timer Counter WD Write Enable TCWD can be written when the TCWE bit is set to 1. When writing data to this bit, the value for bit 7 must be 0. 5 B4WI 1 R/W Bit 4 Write Inhibit The TCSRWE bit can be written only when the write value of the B4WI bit is 0. This bit is always read as 1. 4 TCSRWE 0 R/W Timer Control/Status Register WD Write Enable The WDON and WRST bits can be written when the TCSRWE bit is set to 1. When writing data to this bit, the value for bit 5 must be 0. 3 B2WI 1 R/W Bit 2 Write Inhibit This bit can be written to the WDON bit only when the write value of the B2WI bit is 0. This bit is always read as 1.
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Section 13 Watchdog Timer
Bit 2
Bit Name WDON
Initial Value 0
R/W R/W
Description Watchdog Timer On TCWD starts counting up when WDON is set to 1 and halts when WDON is cleared to 0. [Setting condition] When 1 is written to the WDON bit while writing 0 to the B2WI bit when the TCSRWE bit=1 [Clearing conditions] * * Reset by RES pin When 0 is written to the WDON bit while writing 0 to the B2WI when the TCSRWE bit=1
1
B0WI
1
R/W
Bit 0 Write Inhibit This bit can be written to the WRST bit only when the write value of the B0WI bit is 0. This bit is always read as 1.
0
WRST
0
R/W
Watchdog Timer Reset [Setting condition] When TCWD overflows and an internal reset signal is generated [Clearing conditions] * * Reset by RES pin When 0 is written to the WRST bit while writing 0 to the B0WI bit when the TCSRWE bit=1
13.2.2
Timer Counter WD (TCWD)
TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the internal reset signal is generated and the WRST bit in TCSRWD is set to 1. TCWD is initialized to H'00.
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Section 13 Watchdog Timer
13.2.3
Timer Mode Register WD (TMWD)
TMWD selects the input clock.
Bit 7 to 4 3 2 1 0 Bit Name CKS3 CKS2 CKS1 CKS0 Initial Value All 1 1 1 1 1 R/W R/W R/W R/W R/W Description Reserved These bits are always read as 1. Clock Select 3 to 0 Select the clock to be input to TCWD. 1000: Internal clock: counts on /64 1001: Internal clock: counts on /128 1010: Internal clock: counts on /256 1011: Internal clock: counts on /512 1100: Internal clock: counts on /1024 1101: Internal clock: counts on /2048 1110: Internal clock: counts on /4096 1111: Internal clock: counts on 8192 0XXX: Internal oscillator For the internal oscillator overflow periods, see section 21, Electrical Characteristics. Legend: X: Don't care.
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Section 13 Watchdog Timer
13.3
Operation
The watchdog timer is provided with an 8-bit counter. If 1 is written to WDON while writing 0 to B2WI when the TCSRWE bit in TCSRWD is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write accesses to TCSRWD are required.) When a clock pulse is input after the TCWD count value has reached H'FF, the watchdog timer overflows and an internal reset signal is generated. The internal reset signal is output for a period of 256 osc clock cycles. TCWD is a writable counter, and when a value is set in TCWD, the count-up starts from that value. An overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the TCWD set value. Figure 13.2 shows an example of watchdog timer operation.
Example: With 30ms overflow period when = 4 MHz 4 x 106 8192 x 30 x 10-3 = 14.6
Therefore, 256 - 15 = 241 (H'F1) is set in TCW. TCWD overflow
H'FF H'F1 TCWD count value
H'00 Start H'F1 written to TCWD Internal reset signal 256 osc clock cycles H'F1 written to TCWD Reset generated
Figure 13.2 Watchdog Timer Operation Example
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Section 13 Watchdog Timer
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Section 14 Serial Communication Interface 3 (SCI3)
Section 14 Serial Communication Interface 3 (SCI3)
Serial Communication Interface 3 (SCI3) can handle both asynchronous and clocked synchronous serial communication. In the asynchronous method, serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). Figure 14.1 shows a block diagram of the SCI3.
14.1
Features
* Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected * External clock or on-chip baud rate generator can be selected as a transfer clock source. * Six interrupt sources Transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity error. Asynchronous mode * * * * * Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RxD pin level directly in the case of a framing error
Clocked synchronous mode * Data length: 8 bits * Receive error detection: Overrun errors detected
SCI0010A_000020020200
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Section 14 Serial Communication Interface 3 (SCI3)
SCK3
External clock
Internal clock (/64, /16, /4, ) Baud rate generator
BRC Clock
BRR
Transmit/receive control circuit
SCR3 SSR
TXD
TSR
TDR
RXD
RSR
RDR Interrupt request (TEI, TXI, RXI, ERI)
[Legend] Receive shift register RSR: Receive data register RDR: Transmit shift register TSR: Transmit data register TDR: Serial mode register SMR: SCR3: Serial control register 3 Serial status register SSR: Bit rate register BRR: Bit rate counter BRC:
Figure 14.1 Block Diagram of SCI3
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Internal data bus
SMR
Section 14 Serial Communication Interface 3 (SCI3)
14.2
Input/Output Pins
Table 14.1 shows the SCI3 pin configuration. Table 14.1 Pin Configuration
Pin Name SCI3 clock SCI3 receive data input SCI3 transmit data output Abbreviation SCK3 RXD TXD I/O I/O Input Output Function SCI3 clock input/output SCI3 receive data input SCI3 transmit data output
14.3
Register Descriptions
The SCI3 has the following registers. * * * * * * * * Receive shift register (RSR) Receive data register (RDR) Transmit shift register (TSR) Transmit data register (TDR) Serial mode register (SMR) Serial control register 3 (SCR3) Serial status register (SSR) Bit rate register (BRR)
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Section 14 Serial Communication Interface 3 (SCI3)
14.3.1
Receive Shift Register (RSR)
RSR is a shift register that is used to receive serial data input from the RxD pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 14.3.2 Receive Data Register (RDR)
RDR is an 8-bit register that stores received data. When the SCI3 has received one byte of serial data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR cannot be written to by the CPU. RDR is initialized to H'00. 14.3.3 Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI3 first transfers transmit data from TDR to TSR automatically, then sends the data that starts from the LSB to the TXD pin. TSR cannot be directly accessed by the CPU. 14.3.4 Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The doublebuffered structure of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR during transmission of one-frame data, the SCI3 transfers the written data to TSR to continue transmission. To achieve reliable serial transmission, write transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is initialized to H'FF.
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Section 14 Serial Communication Interface 3 (SCI3)
14.3.5
Serial Mode Register (SMR)
SMR is used to set the SCI3's serial transfer format and select the on-chip baud rate generator clock source.
Bit 7 Bit Name COM Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. 4 PM 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits For reception, only the first stop bit is checked, regardless of the value in the bit. If the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 MP 0 R/W Multiprocessor Mode When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and PM bit settings are invalid. In clocked synchronous mode, this bit should be cleared to 0.
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Section 14 Serial Communication Interface 3 (SCI3)
Bit 1 0
Bit Name CKS1 CKS0
Initial Value 0 0
R/W R/W R/W
Description Clock Select 0 and 1 These bits select the clock source for the on-chip baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 14.3.8, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 14.3.8, Bit Rate Register (BRR)).
14.3.6
Serial Control Register 3 (SCR3)
SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is also used to select the transfer clock source. For details on interrupt requests, refer to section 14.7, Interrupts.
Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, the TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 TE RE 0 0 R/W R/W Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled.
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Section 14 Serial Communication Interface 3 (SCI3)
Bit 3
Bit Name MPIE
Initial Value 0
R/W R/W
Description Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and OER status flags in SSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, refer to section 14.6, Multiprocessor Communication Function.
2
TEIE
0
R/W
Transmit End Interrupt Enable When this bit is set to 1, the TEI interrupt request is enabled.
1 0
CKE1 CKE0
0 0
R/W R/W
Clock Enable 0 and 1 Selects the clock source. Asynchronous mode: 00: Internal baud rate generator 01: Internal baud rate generator Outputs a clock of the same frequency as the bit rate from the SCK3 pin. 10: External clock Inputs a clock with a frequency 16 times the bit rate from the SCK3 pin. 11: Reserved Clocked synchronous mode: 00: Internal clock (SCK3 pin functions as clock output) 01: Reserved 10: External clock (SCK3 pin functions as clock input) 11: Reserved
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Section 14 Serial Communication Interface 3 (SCI3)
14.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared.
Bit 7 Bit Name TDRE Initial Value 1 R/W R/W Description Transmit Data Register Empty Displays whether TDR contains transmit data. [Setting conditions] * * * * 6 RDRF 0 R/W When the TE bit in SCR3 is 0 When data is transferred from TDR to TSR When 0 is written to TDRE after reading TDRE = 1 When the transmit data is written to TDR
[Clearing conditions]
Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 When data is read from RDR
[Clearing conditions] * * 5 OER 0 R/W
Overrun Error [Setting condition] * * When an overrun error occurs in reception When 0 is written to OER after reading OER = 1 [Clearing condition]
4
FER
0
R/W
Framing Error [Setting condition] * * When a framing error occurs in reception When 0 is written to FER after reading FER = 1 [Clearing condition]
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Section 14 Serial Communication Interface 3 (SCI3)
Bit 3
Bit Name PER
Initial Value 0
R/W R/W
Description Parity Error [Setting condition] * * When a parity error is generated during reception When 0 is written to PER after reading PER = 1 [Clearing condition]
2
TEND
1
R
Transmit End [Setting conditions] * * When the TE bit in SCR3 is 0 When TDRE = 1 at transmission of the last bit of a 1byte serial transmit character When 0 is written to TEND after reading TEND = 1 When the transmit data is written to TDR
[Clearing conditions] * * 1 MPBR 0 R
Multiprocessor Bit Receive MPBR stores the multiprocessor bit in the receive character data. When the RE bit in SCR3 is cleared to 0, its previous state is retained.
0
MPBT
0
R/W
Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to the transmit character data.
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Section 14 Serial Communication Interface 3 (SCI3)
14.3.8
Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 14.2 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in asynchronous mode. Table 14.3 shows the maximum bit rate for each frequency in asynchronous mode. The values shown in both tables 14.2 and 14.3 are values in active (highspeed) mode. Table 14.4 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 in SMR in clocked synchronous mode. The values shown in table 14.4 are values in active (high-speed) mode. The N setting in BRR and error for other operating frequencies and bit rates can be obtained by the following formulas: [Asynchronous Mode]
N= x 106 - 1 64 x 22n-1 x B
Error (%) =
x 106 - 1 x 100 (N + 1) x B x 64 x 22n-1
[Clocked Synchronous Mode]
N= x 106 - 1 8 x 22n-1 x B
Note: B: N: : n:
Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (MHz) CKS1 and CKS0 setting for SMR (0 N 3)
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Section 14 Serial Communication Interface 3 (SCI3)
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
Operating Frequency (MHz) 2 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 0 0 0 0 N 141 103 207 103 51 25 12 6 2 1 1 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -6.99 8.51 0.00 -18.62 n 1 1 0 0 0 0 0 0 0 0 0 2.097152 N 148 108 217 108 54 26 13 6 2 1 1 Error (%) -0.04 0.21 0.21 0.21 -0.70 1.14 -2.48 -2.48 13.78 4.86 -14.67 n 1 1 0 0 0 0 0 0 0 0 0 2.4576 N 174 127 255 127 63 31 15 7 3 1 1 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 22.88 0.00 n 1 1 1 0 0 0 0 0 0 0 -- N 212 155 77 155 77 38 19 9 4 2 -- 3 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 --
Legend: : A setting is available but error occurs Operating Frequency (MHz) 3.6864 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 -- 0 N 64 191 95 191 95 47 23 11 5 -- 2 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 1 1 0 0 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 6 3 2 4 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -6.99 0.00 8.51 n 2 1 1 0 0 0 0 0 0 0 0 4.9152 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73
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Section 14 Serial Communication Interface 3 (SCI3)
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
Operating Frequency (MHz) 6 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 n 2 2 1 1 0 0 0 0 0 0 0 6.144 N 108 79 159 79 159 79 39 19 9 5 4 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 0 0 7.3728 N 130 95 191 95 191 95 47 23 11 6 5 Error (%) -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 6 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -6.99
Operating Frequency (MHz) 9.8304 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.00 -2.34 n 2 2 2 1 1 0 0 0 0 0 0 12.888 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00
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Section 14 Serial Communication Interface 3 (SCI3)
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3)
Operating Frequency (MHz) 14 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 -- N 248 181 90 181 90 181 90 45 22 13 -- Error (%) -0.17 0.16 0.16 0.16 0.16 0.16 0.16 -0.93 -0.93 0.00 -- n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16
Operating Frequency (MHz) 18 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 28 17 14 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.96 1.02 0.00 -2.34 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73
Legend: --: A setting is available but error occurs.
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Section 14 Serial Communication Interface 3 (SCI3)
Table 14.3 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
(MHz) 2 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 Maximum Bit Rate (bit/s) 62500 76800 93750 115200 125000 153600 156250 187500 192000 230400 n 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 (MHz) 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 20 Maximum Bit Rate (bit/s) 250000 307200 312500 375000 384000 437500 460800 500000 537600 562500 625000 n 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0
2.097152 65536
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Section 14 Serial Communication Interface 3 (SCI3)
Table 14.4 Examples of BBR Setting for Various Bit Rates (Clocked Synchronous Mode) (1)
Operating Frequency (MHz) Bit Rate (bit/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2M 2.5M 4M Legend: Blank : No setting is available. -- : A setting is available but error occurs. * : Continuous transfer is not possible. 2 n 3 2 1 1 0 0 0 0 0 0 0 0 N 70 124 249 124 199 99 49 19 9 4 1 0* n -- 2 2 1 1 0 0 0 0 0 0 0 0 4 N -- 249 124 249 99 199 99 39 19 9 3 1 0* n -- 3 2 2 1 1 0 0 0 0 0 0 0 0 8 N -- 124 249 124 199 99 199 79 39 19 7 3 1 0* n -- -- -- -- 1 1 0 0 0 0 0 0 -- -- 0 10 N -- -- -- -- 249 124 249 99 49 24 9 4 -- -- 0* 3 3 2 2 1 1 0 0 0 0 0 0 0 -- 0 249 124 249 99 199 99 159 79 39 15 7 3 1 -- 0* n 16 N
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Section 14 Serial Communication Interface 3 (SCI3)
Table 14.4 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2)
Operating Frequency (MHz) Bit Rate (bit/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2M 2.5M 4M 18 n -- -- 3 3 2 1 1 0 0 0 0 0 0 -- -- -- N -- -- 140 69 112 224 112 179 89 44 17 8 4 -- -- -- n -- -- 3 3 2 1 1 0 0 0 0 0 0 -- 0 -- 20 N -- -- 155 77 124 249 124 199 99 49 19 9 4 -- 1 --
Legend: Blank : No setting is available. -- : A setting is available but error occurs. * : Continuous transfer is not possible.
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Section 14 Serial Communication Interface 3 (SCI3)
14.4
Operation in Asynchronous Mode
Figure 14.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units, enabling full duplex. Both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer.
LSB
Serial Start data bit
MSB Transmit/receive data
Parity bit
1
Stop bit
Mark state
1 bit
7 or 8 bits
1 bit, or none
1 or 2 bits
One unit of transfer data (character or frame)
Figure 14.2 Data Format in Asynchronous Communication 14.4.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK3 pin can be selected as the SCI3's serial clock source, according to the setting of the COM bit in SMR and the CKE0 and CKE1 bits in SCR3. When an external clock is input at the SCK3 pin, the clock frequency should be 16 times the bit rate used. When the SCI3 is operated on an internal clock, the clock can be output from the SCK3 pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 14.3.
Clock Serial data 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 character (frame)
Figure 14.3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)
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Section 14 Serial Communication Interface 3 (SCI3)
14.4.2
SCI3 Initialization
Follow the flowchart as shown in figure 14.4 to initialize the SCI3. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization.
[1] Start initialization Set the clock selection in SCR3. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock output is selected in asynchronous mode, clock is output immediately after CKE1 and CKE0 settings are made. When the clock output is selected at reception in clocked synchronous mode, clock is output immediately after CKE1, CKE0, and RE are set to 1. [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR3 to 1, and set RIE, TIE, TEIE, and MPIE bits. For transmit (TE=1), also set the TxD bit in PMR1. [4] Set the data transfer format in SMR. Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. Wait at least one bit interval, then set the TE bit or RE bit in SCR3 to 1. RE settings enable the RXD pin to be used. For transmission, set the TXD bit in PMR1 to 1 to enable the TXD output pin to be used. Also set the RIE, TIE, TEIE, and MPIE bits, depending on whether interrupts are required. In asynchronous mode, the bits are marked at transmission and idled at reception to wait for the start bit.
Clear TE and RE bits in SCR3 to 0 [1] Set CKE1 and CKE0 bits in SCR3
Set data transfer format in SMR
[2]
Set value in BRR Wait
[3]
[4]

Figure 14.4 Sample SCI3 Initialization Flowchart
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Section 14 Serial Communication Interface 3 (SCI3)
14.4.3
Data Transmission
Figure 14.5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a TXI interrupt request is generated. Continuous transmission is possible because the TXI interrupt routine writes next transmit data to TDR before transmission of the current transmit data has been completed. 3. The SCI3 checks the TDRE flag at the timing for sending the stop bit. 4. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 5. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered, in which 1 is output. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt request is generated. 6. Figure 14.6 shows a sample flowchart for transmission in asynchronous mode.
Start bit Serial data 1 0 D0 D1 1 frame Transmit data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Transmit data D1 1 frame D7 Parity Stop bit bit 0/1 1 Mark state 1
TDRE TEND TXI interrupt LSI operation request generated User processing TDRE flag cleared to 0 Data written to TDR TXI interrupt request generated TEI interrupt request generated
Figure 14.5 Example SCI3 Operation in Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)
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Section 14 Serial Communication Interface 3 (SCI3)
Start transmission
[1]
Read TDRE flag in SSR
No TDRE = 1 Yes
Write transmit data to TDR
[2]
Yes All data transmitted? No
[1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. [2] To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. [3] To output a break in serial transmission, after setting PCR to 1 and PDR to 0, clear TxD in PMR1 to 0, then clear the TE bit in SCR3 to 0.
Read TEND flag in SSR
No TEND = 1 Yes No Break output? Yes Clear PDR to 0 and set PCR to 1
[3]
Clear TE bit in SCR3 to 0
Figure 14.6 Sample Serial Transmission Flowchart (Asynchronous Mode)
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Section 14 Serial Communication Interface 3 (SCI3)
14.4.4
Serial Data Reception
Figure 14.7 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives data in RSR, and checks the parity bit and stop bit. 2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated. 5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is generated. Continuous reception is possible because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has been completed.
Start bit Serial data 1 0 D0 D1 1 frame Receive data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Receive data D1 1 frame D7 Parity Stop bit bit 0/1 0 Mark state (idle state) 1
RDRF FER LSI operation User processing RXI request RDRF cleared to 0 RDR data read 0 stop bit detected ERI request in response to framing error Framing error processing
Figure 14.7 Example SCI3 Operation in Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)
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Section 14 Serial Communication Interface 3 (SCI3)
Table 14.5 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.8 shows a sample flowchart for serial data reception. Table 14.5 SSR Status Flags and Receive Data Handling
SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * OER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error
The RDRF flag retains the state it had before data reception.
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Section 14 Serial Communication Interface 3 (SCI3)
Start reception
Read OER, PER, and FER flags in SSR
[1]
Yes OER+PER+FER = 1 [4] No Error processing (Continued on next page) Read RDRF flag in SSR No RDRF = 1 Yes [2]
Read receive data in RDR
[1] Read the OER, PER, and FER flags in SSR to identify the error. If a receive error occurs, performs the appropriate error processing. [2] Read SSR and check that RDRF = 1, then read the receive data in RDR. The RDRF flag is cleared automatically. [3] To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag and read RDR. The RDRF flag is cleared automatically. [4] If a receive error occurs, read the OER, PER, and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the OER, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1. In the case of a framing error, a break can be detected by reading the value of the input port corresponding to the RxD pin.
Yes All data received? (A) No Clear RE bit in SCR3 to 0 [3]
Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous mode) (1)
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Section 14 Serial Communication Interface 3 (SCI3)
[4] Error processing
No OER = 1 Yes Overrun error processing
No FER = 1 Yes Yes Break? No Framing error processing
No PER = 1 Yes Parity error processing (A) Clear OER, PER, and FER flags in SSR to 0

Figure 14.8 Sample Serial Reception Data Flowchart (2)
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Section 14 Serial Communication Interface 3 (SCI3)
14.5
Operation in Clocked Synchronous Mode
Figure 14.9 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. In clocked synchronous mode, the SCI3 receives data in synchronous with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex communication through the use of a common clock. Both the transmitter and the receiver also have a doublebuffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer.
8-bit One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care *
Figure 14.9 Data Format in Clocked Synchronous Communication 14.5.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK3 pin can be selected, according to the setting of the COM bit in SMR and CKE0 and CKE1 bits in SCR3. When the SCI3 is operated on an internal clock, the serial clock is output from the SCK3 pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. 14.5.2 SCI3 Initialization
Before transmitting and receiving data, the SCI3 should be initialized as described in a sample flowchart in figure 14.4.
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Section 14 Serial Communication Interface 3 (SCI3)
14.5.3
Serial Data Transmission
Figure 14.10 shows an example of SCI3 operation for transmission in clocked synchronous mode. In serial transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR3 is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the TXD pin. 4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the output state of the last bit. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt request is generated. 7. The SCK3 pin is fixed high. Figure 14.11 shows a sample flowchart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1. Make sure that the receive error flags are cleared to 0 before starting transmission.
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Section 14 Serial Communication Interface 3 (SCI3)
Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
1 frame TDRE TEND LSI TXI interrupt operation request generated User processing TDRE flag cleared to 0 Data written to TDR
1 frame
TXI interrupt request generated
TEI interrupt request generated
Figure 14.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode
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Section 14 Serial Communication Interface 3 (SCI3)
Start transmission
[1]
[1]
Read TDRE flag in SSR
No TDRE = 1 Yes
[2]
Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0 and clocks are output to start the data transmission. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0.
Write transmit data to TDR
[2]
All data transmitted? No
Yes
Read TEND flag in SSR
No TEND = 1 Yes Clear TE bit in SCR3 to 0
Figure 14.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)
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Section 14 Serial Communication Interface 3 (SCI3)
14.5.4
Serial Data Reception (Clocked Synchronous Mode)
Figure 14.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In serial reception, the SCI3 operates as described below. 1. The SCI3 performs internal initialization synchronous with a synchronous clock input or output, starts receiving data. 2. The SCI3 stores the received data in RSR. 3. If an overrun error occurs (when reception of the next data is completed while the RDRF flag in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the RDRF flag remains to be set to 1. 4. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is generated.
Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
1 frame RDRF OER LSI operation User processing RXI interrupt request generated RDRF flag cleared to 0 RDR data read
1 frame
RXI interrupt request generated
ERI interrupt request generated by overrun error Overrun error processing
RDR data has not been read (RDRF = 1)
Figure 14.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.13 shows a sample flowchart for serial data reception.
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Section 14 Serial Communication Interface 3 (SCI3)
Start reception [1] Read OER flag in SSR [1] [2] Yes OER = 1 [4] No Error processing (Continued below) Read RDRF flag in SSR [2] [4] RDRF = 1 Yes [3] Read the OER flag in SSR to determine if there is an error. If an overrun error has occurred, execute overrun error processing. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF flag is automatically cleared to 0. To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag and reading RDR should be finished. When data is read from RDR, the RDRF flag is automatically cleared to 0. If an overrun error occurs, read the OER flag in SSR, and after performing the appropriate error processing, clear the OER flag to 0. Reception cannot be resumed if the OER flag is set to 1.
No
Read receive data in RDR
Yes All data received? No Clear RE bit in SCR3 to 0 [3]
[4]
Error processing
Overrun error processing
Clear OER flag in SSR to 0
Figure 14.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)
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Section 14 Serial Communication Interface 3 (SCI3)
14.5.5
Simultaneous Serial Data Transmission and Reception
Figure 14.14 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished reception, clear RE to 0. Then after checking that the RDRF and receive error flags (OER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction.
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Section 14 Serial Communication Interface 3 (SCI3)
Start transmission/reception
[1]
Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR
[1]
Read OER flag in SSR Yes [4] Error processing
OER = 1 No
Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR
[2]
Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. [2] Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF flag is automatically cleared to 0. [3] To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. When data is read from RDR, the RDRF flag is automatically cleared to 0. [4] If an overrun error occurs, read the OER flag in SSR, and after performing the appropriate error processing, clear the OER flag to 0. Transmission/reception cannot be resumed if the OER flag is set to 1. For overrun error processing, see figure 14.13.
Yes All data received? No [3]
Clear TE and RE bits in SCR to 0

Figure 14.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations (Clocked Synchronous Mode)
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Section 14 Serial Communication Interface 3 (SCI3)
14.6
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles; an ID transmission cycle that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 14.15 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI3 uses the MPIE bit in SCR3 to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and OER to 1, are inhibited until data with a 1 multiprocessor bit is received. On reception of a receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode.
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Section 14 Serial Communication Interface 3 (SCI3)
Transmitting station Serial transmission line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) H'01 (MPB = 1) Receiving station C (ID = 03) H'AA (MPB = 0) Receiving station D (ID = 04)
ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID [Legend] MPB: Multiprocessor bit
Figure 14.15 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) 14.6.1 Multiprocessor Serial Data Transmission
Figure 14.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same as those in asynchronous mode.
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Section 14 Serial Communication Interface 3 (SCI3)
Start transmission [1] [1] Read TDRE flag in SSR Read SSR and check that the TDRE flag is set to 1, set the MPBT bit in SSR to 0 or 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. To output a break in serial transmission, set the port PCR to 1, clear PDR to 0, then clear the TE bit in SCR3 to 0.
No TDRE = 1 [2] Yes
Set MPBT bit in SSR
[3] Write transmit data to TDR
Yes [2] All data transmitted? No
Read TEND flag in SSR
No TEND = 1 Yes No [3] Break output? Yes
Clear PDR to 0 and set PCR to 1
Clear TE bit in SCR3 to 0

Figure 14.16 Sample Multiprocessor Serial Transmission Flowchart
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Section 14 Serial Communication Interface 3 (SCI3)
14.6.2
Multiprocessor Serial Data Reception
Figure 14.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI3 operations are the same as in asynchronous mode. Figure 14.18 shows an example of SCI3 operation for multiprocessor format reception.
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Section 14 Serial Communication Interface 3 (SCI3)
Start reception
[1] [2] [1] [2] Yes [3]
Set MPIE bit in SCR3 to 1 Read OER and FER flags in SSR
FER+OER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR No This station's ID? Yes Read OER and FER flags in SSR Yes FER+OER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR Yes All data received? No [A] Clear RE bit in SCR3 to 0 [4] [3] [4] [5]
Set the MPIE bit in SCR3 to 1. Read OER and FER in SSR to check for errors. Receive error processing is performed in cases where a receive error occurs. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again. When data is read from RDR, the RDRF flag is automatically cleared to 0. Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. If a receive error occurs, read the OER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the OER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value.
[5] Error processing (Continued on next page)
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (1)
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Section 14 Serial Communication Interface 3 (SCI3)
[5]
Error processing
No OER = 1 Yes Overrun error processing
No FER = 1 Yes Yes Break? No Framing error processing [A]
Clear OER, and FER flags in SSR to 0

Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (2)
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Section 14 Serial Communication Interface 3 (SCI3)
Start bit Serial data 1 0 D0
Receive data (ID1) D1 1 frame D7
MPB 1
Stop Start bit bit 1 0 D0
Receive data (Data1) D1 1 frame D7
MPB 0
Stop bit 1
Mark state (idle state) 1
MPIE
RDRF RDR value LSI operation User processing RXI interrupt request MPIE cleared to 0 RDRF flag cleared to 0 RDR data read When data is not this station's ID, MPIE is set to 1 again ID1
RXI interrupt request is not generated, and RDR retains its state
(a) When data does not match this receiver's ID
Start bit Serial data 1 0 D0
Receive data (ID2) D1 1 frame D7
MPB 1
Stop Start bit bit 1 0 D0
Receive data (Data2) D1 1 frame D7
MPB 0
Stop bit 1
Mark state (idle state) 1
MPIE
RDRF RDR value LSI operation User processing ID1 ID2 Data2
RXI interrupt request MPIE cleared to 0
RDRF flag cleared to 0 RDR data read
RXI interrupt request When data is this station's ID, reception is continued
RDRF flag cleared to 0 RDR data read MPIE set to 1 again
(b) When data matches this receiver's ID
Figure 14.18 Example of SCI3 Operation in Reception Using Multiprocessor Format (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
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Section 14 Serial Communication Interface 3 (SCI3)
14.7
Interrupts
The SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 14.6 shows the interrupt sources. Table 14.6 SCI3 Interrupt Requests
Interrupt Requests Receive Data Full Transmit Data Empty Transmission End Receive Error Abbreviation RXI TXI TEI ERI Interrupt Sources Setting RDRF in SSR Setting TDRE in SSR Setting TEND in SSR Setting OER, FER, and PER in SSR
The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR3 is set to 1 before transferring the transmit data to TDR, a TXI interrupt request is generated even if the transmit data is not ready. The initial value of the TEND flag in SSR is 1. Thus, when the TEIE bit in SCR3 is set to 1 before transferring the transmit data to TDR, a TEI interrupt request is generated even if the transmit data has not been sent. It is possible to make use of the most of these interrupt requests efficiently by transferring the transmit data to TDR in the interrupt routine. To prevent the generation of these interrupt requests (TXI and TEI), set the enable bits (TIE and TEIE) that correspond to these interrupt requests to 1, after transferring the transmit data to TDR.
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Section 14 Serial Communication Interface 3 (SCI3)
14.8
14.8.1
Usage Notes
Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0, setting the FER flag, and possibly the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 14.8.2 Mark State and Break Sending
When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by PCR and PDR. This can be used to set the TxD pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both PCR and PDR to 1. As TE is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set PCR to 1 and PDR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 14.8.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.
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Section 14 Serial Communication Interface 3 (SCI3)
14.8.4
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 14.19. Thus, the reception margin in asynchronous mode is given by formula (1) below.
1 D - 0.5 M = (0.5 - )- - (L - 0.5) F x 100(%) 2N N
... Formula (1) Where N D L F : Ratio of bit rate to clock (N = 16) : Clock duty (D = 0.5 to 1.0) : Frame length (L = 9 to 12) : Absolute value of clock rate deviation
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula. M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design.
16 clocks 8 clocks 0 Internal basic clock Receive data (RxD) Synchronization sampling timing Data sampling timing 7 15 0 7 15 0
Start bit
D0
D1
Figure 14.19 Receive Data Sampling Timing in Asynchronous Mode
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Section 15 I C Bus Interface 2 (IIC2)
2
Section 15 I2C Bus Interface 2 (IIC2)
The I2C bus interface 2 conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. Figure 15.1 shows a block diagram of the I2C bus interface 2. Figure 15.2 shows an example of I/O pin connections to external circuits.
15.1
Features
* Selection of I2C format or clocked synchronous serial format * Continuous transmission/reception Since the shift register, transmit data register, and receive data register are independent from each other, the continuous transmission/reception can be performed. I2C bus format * Start and stop conditions generated automatically in master mode * Selection of acknowledge output levels when receiving * Automatic loading of acknowledge bit when transmitting * Bit synchronization/wait function In master mode, the state of SCL is monitored per bit, and the timing is synchronized automatically. If transmission/reception is not yet possible, set the SCL to low until preparations are completed. * Six interrupt sources Transmit data empty (including slave-address match), transmit end, receive data full (including slave-address match), arbitration lost, NACK detection, and stop condition detection * Direct bus drive Two pins, SCL and SDA pins, function as NMOS open-drain outputs when the bus drive function is selected. Clocked synchronous format * Four interrupt sources Transmit-data-empty, transmit-end, receive-data-full, and overrun error
IFIIC10A_000020020200
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Section 15 I C Bus Interface 2 (IIC2)
2
Transfer clock generation circuit
SCL
Output control
Transmission/ reception control circuit
ICCR1 ICCR2 ICMR
Noise canceler ICDRT SAR
SDA
Output control
ICDRS
Noise canceler
Address comparator ICDRR Bus state decision circuit Arbitration decision circuit ICIER
ICSR
[Legend] ICCR1 : I2C bus control register 1 ICCR2 : I2C bus control register 2 ICMR : I2C bus mode register ICSR : I2C bus status register ICIER : I2C bus interrupt enable register ICDRT : I2C bus transmit data register ICDRR : I2C bus receive data register ICDRS : I2C bus shift register SAR : Slave address register
Interrupt generator
Figure 15.1 Block Diagram of I2C Bus Interface 2
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Internal data bus
Interrupt request
Section 15 I C Bus Interface 2 (IIC2)
2
Vcc
Vcc
SCL in SCL out
SCL
SCL
SDA in SDA out
SDA
SDA
SCL SDA
(Master)
SCL in SCL out
SCL in SCL out
SDA in SDA out (Slave 1)
SDA in SDA out (Slave 2)
Figure 15.2 External Circuit Connections of I/O Pins
15.2
Input/Output Pins
Table 15.1 summarizes the input/output pins used by the I2C bus interface 2. Table 15.1 I2C Bus Interface Pins
Name Serial clock Serial data Abbreviation SCL SDA I/O I/O I/O Function IIC serial clock input/output IIC serial data input/output
15.3
Register Descriptions
The I2C bus interface 2 has the following registers: * * * * * * I2C bus control register 1 (ICCR1) I2C bus control register 2 (ICCR2) I2C bus mode register (ICMR) I2C bus interrupt enable register (ICIER) I2C bus status register (ICSR) I2C bus slave address register (SAR)
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SCL SDA
Section 15 I C Bus Interface 2 (IIC2)
2
* I2C bus transmit data register (ICDRT) * I2C bus receive data register (ICDRR) * I2C bus shift register (ICDRS) 15.3.1 I2C Bus Control Register 1 (ICCR1)
ICCR1 enables or disables the I2C bus interface 2, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode.
Bit 7 Bit Name ICE Initial Value 0 R/W R/W Description I2C Bus Interface Enable 0: This module is halted. (SCL and SDA pins are set to port function.) 1: This bit is enabled for transfer operations. (SCL and SDA pins are bus drive state.) 6 RCVD 0 R/W Reception Disable This bit enables or disables the next operation when TRS is 0 and ICDRR is read. 0: Enables next reception 1: Disables next reception 5 4 MST TRS 0 0 R/W R/W Master/Slave Select Transmit/Receive Select In master mode with the I2C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames. After data receive has been started in slave receive mode, when the first seven bits of the receive data agree with the slave address that is set to SAR and the eighth bit is 1, TRS is automatically set to 1. If an overrun error occurs in master mode with the clock synchronous serial format, MST is cleared to 0 and slave receive mode is entered. Operating modes are described below according to MST and TRS combination. When clocked synchronous serial format is selected and MST is 1, clock is output. 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode
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Section 15 I C Bus Interface 2 (IIC2)
2
Bit 3 2 1 0
Bit Name CKS3 CKS2 CKS1 CKS0
Initial Value 0 0 0 0
R/W R/W R/W R/W R/W
Description Transfer Clock Select 3 to 0 These bits should be set according to the necessary transfer rate (see table 15.2) in master mode. In slave mode, these bits are used for reservation of the setup time in transmit mode. The time is 10 tcyc when CKS3 = 0 and 20 tcyc when CKS3 = 1.
Table 15.2 Transfer Rate
Bit 3 CKS3 0 Bit 2 CKS2 0 Bit 1 CKS1 0 1 1 0 1 1 0 0 1 1 0 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock /28 /40 /48 /64 /80 /100 /112 /128 /56 /80 /96 /128 /160 /200 /224 /256
= 5 MHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz 89.3 kHz 62.5 kHz 52.1 kHz 39.1 kHz 31.3 kHz 25.0 kHz 22.3 kHz 19.5 kHz = 8 MHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz 143 kHz 100 kHz 83.3 kHz 62.5 kHz 50.0 kHz 40.0 kHz 35.7 kHz 31.3 kHz
Transfer Rate
= 10 MHz = 16 MHz = 20 MHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz 571 kHz 400 kHz 333 kHz 250 kHz 200 kHz 160 kHz 143 kHz 125 kHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz 714 kHz 500 kHz 417 kHz 313 kHz 250 kHz 200 kHz 179 kHz 156 kHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz
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Section 15 I C Bus Interface 2 (IIC2)
2
15.3.2
I2C Bus Control Register 2 (ICCR2)
ICCR1 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in the control part of the I2C bus interface 2.
Bit 7 Bit Name BBSY Initial Value 0 R/W R/W Description Bus Busy This bit enables to confirm whether the I C bus is occupied or released and to issue start/stop conditions in master mode. With the clocked synchronous serial 2 format, this bit has no meaning. With the I C bus format, this bit is set to 1 when the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. This bit is cleared to 0 when the SDA level changes from low to high under the condition of SCL = high, assuming that the stop condition has been issued. Write 1 to BBSY and 0 to SCP to issue a start condition. Follow this procedure when also retransmitting a start condition. Write 0 in BBSY and 0 in SCP to issue a stop condition. To issue start/stop conditions, use the MOV instruction. 6 SCP 1 W Start/Stop Issue Condition Disable The SCP bit controls the issue of start/stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. If 1 is written, the data is not stored. 5 SDAO 1 R/W SDA Output Value Control This bit is used with SDAOP when modifying output level of SDA. This bit should not be manipulated during transfer. 0: When reading, SDA pin outputs low. When writing, SDA pin is changed to output low. 1: When reading, SDA pin outputs high. When writing, SDA pin is changed to output Hi-Z (outputs high by external pull-up resistance).
2
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Section 15 I C Bus Interface 2 (IIC2)
2
Bit 4
Bit Name SDAOP
Initial Value 1
R/W R/W
Description SDAO Write Protect This bit controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0 by the MOV instruction. This bit is always read as 1. This bit monitors SCL output level. When SCLO is 1, SCL pin outputs high. When SCLO is 0, SCL pin outputs low. Reserved This bit is always read as 1, and cannot be modified. IIC Control Part Reset This bit resets the control part except for I2C registers. If this bit is set to 1 when hang-up occurs because of 2 2 communication failure during I C operation, I C control part can be reset without setting ports and initializing registers. Reserved This bit is always read as 1, and cannot be modified.
3 2 1
SCLO IICRST
1 1 0
R R/W
0
1
15.3.3
I2C Bus Mode Register (ICMR)
ICMR selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the transfer bit count.
Bit 7 Bit Name MLS Initial Value 0 R/W R/W Description MSB-First/LSB-First Select 0: MSB-first 1: LSB-first Set this bit to 0 when the I2C bus format is used. Wait Insertion Bit In master mode with the I2C bus format, this bit selects whether to insert a wait after data transfer except the acknowledge bit. When WAIT is set to 1, after the fall of the clock for the final data bit, low period is extended for two transfer clocks. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. The setting of this bit is invalid in slave mode with the I C bus format or with the clocked synchronous serial format.
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2
6
WAIT
0
R/W
Section 15 I C Bus Interface 2 (IIC2)
2
Bit 5, 4 3
Bit Name BCWP
Initial Value All 1 1
R/W R/W
Description Reserved These bits are always read as 1, and cannot be modified. BC Write Protect This bit controls the BC2 to BC0 modifications. When modifying BC2 to BC0, this bit should be cleared to 0 and use the MOV instruction. In clock synchronous serial mode, BC should not be modified. 0: When writing, values of BC2 to BC0 are set. 1: When reading, 1 is always read. When writing, settings of BC2 to BC0 are invalid.
2 1 0
BC2 BC1 BC0
0 0 0
R/W R/W R/W
Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits is indicated. With the I2C bus format, the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL pin is low. The value returns to 000 at the end of a data transfer, including the acknowledge bit. With the clock synchronous serial format, these bits should not be modified. I C Bus Format 000: 9 bits 001: 2 bits 010: 3 bits 011: 4 bits 100: 5 bits 101: 6 bits 110: 7 bits 111: 8 bits
2
Clock Synchronous Serial Format 000: 8 bits 001: 1 bits 010: 2 bits 011: 3 bits 100: 4 bits 101: 5 bits 110: 6 bits 111: 7 bits
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15.3.4
I2C Bus Interrupt Enable Register (ICIER)
ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be received.
Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty interrupt (TXI). 0: Transmit data empty interrupt request (TXI) is disabled. 1: Transmit data empty interrupt request (TXI) is enabled. 6 TEIE 0 R/W Transmit End Interrupt Enable This bit enables or disables the transmit end interrupt (TEI) at the rising of the ninth clock while the TDRE bit in ICSR is 1. TEI can be canceled by clearing the TEND bit or the TEIE bit to 0. 0: Transmit end interrupt request (TEI) is disabled. 1: Transmit end interrupt request (TEI) is enabled. 5 RIE 0 R/W Receive Interrupt Enable This bit enables or disables the receive data full interrupt request (RXI) and the overrun error interrupt request (ERI) with the clocked synchronous format, when a receive data is transferred from ICDRS to ICDRR and the RDRF bit in ICSR is set to 1. RXI can be canceled by clearing the RDRF or RIE bit to 0. 0: Receive data full interrupt request (RXI) and overrun error interrupt request (ERI) with the clocked synchronous format are disabled. 1: Receive data full interrupt request (RXI) and overrun error interrupt request (ERI) with the clocked synchronous format are enabled. 4 NAKIE 0 R/W NACK Receive Interrupt Enable This bit enables or disables the NACK receive interrupt request (NAKI) and the overrun error (setting of the OVE bit in ICSR) interrupt request (ERI) with the clocked synchronous format, when the NACKF and AL bits in ICSR are set to 1. NAKI can be canceled by clearing the NACKF, OVE, or NAKIE bit to 0. 0: NACK receive interrupt request (NAKI) is disabled. 1: NACK receive interrupt request (NAKI) is enabled.
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Section 15 I C Bus Interface 2 (IIC2)
2
Bit 3
Bit Name STIE
Initial Value 0
R/W R/W
Description Stop Condition Detection Interrupt Enable 0: Stop condition detection interrupt request (STPI) is disabled. 1: Stop condition detection interrupt request (STPI) is enabled.
2
ACKE
0
R/W
Acknowledge Bit Judgement Select 0: The value of the receive acknowledge bit is ignored, and continuous transfer is performed. 1: If the receive acknowledge bit is 1, continuous transfer is halted.
1
ACKBR
0
R
Receive Acknowledge In transmit mode, this bit stores the acknowledge data that are returned by the receive device. This bit cannot be modified. 0: Receive acknowledge = 0 1: Receive acknowledge = 1
0
ACKBT
0
R/W
Transmit Acknowledge In receive mode, this bit specifies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing. 1: 1 is sent at the acknowledge timing.
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Section 15 I C Bus Interface 2 (IIC2)
2
15.3.5
I2C Bus Status Register (ICSR)
ICSR performs confirmation of interrupt request flags and status.
Bit 7 Bit Name TDRE Initial Value 0 R/W R/W Description Transmit Data Register Empty [Setting conditions] * * * * When data is transferred from ICDRT to ICDRS and ICDRT becomes empty When TRS is set When a start condition (including re-transfer) has been issued When transmit mode is entered from receive mode in slave mode When 0 is written in TDRE after reading TDRE = 1 When data is written to ICDRT with an instruction
[Clearing conditions] * * 6 TEND 0 R/W
Transmit End [Setting conditions] * * When the ninth clock of SCL rises with the I C bus format while the TDRE flag is 1 When the final bit of transmit frame is sent with the clock synchronous serial format When 0 is written in TEND after reading TEND = 1 When data is written to ICDRT with an instruction
2
[Clearing conditions] * * 5 RDRF 0 R/W
Receive Data Register Full [Setting condition] * When a receive data is transferred from ICDRS to ICDRR When 0 is written in RDRF after reading RDRF = 1 When ICDRR is read with an instruction
[Clearing conditions] * *
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Section 15 I C Bus Interface 2 (IIC2)
2
Bit 4
Bit Name NACKF
Initial Value 0
R/W R/W
Description No Acknowledge Detection Flag [Setting condition] * When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1
[Clearing condition] * 3 STOP 0 R/W When 0 is written in NACKF after reading NACKF = 1
Stop Condition Detection Flag [Setting conditions] * * In master mode, when a stop condition is detected after frame transfer In slave mode, when a stop condition is detected after the general call address or the first byte slave address, next to detection of start condition, accords with the address set in SAR When 0 is written in STOP after reading STOP = 1
[Clearing condition] *
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Section 15 I C Bus Interface 2 (IIC2)
2
Bit 2
Bit Name AL/OVE
Initial Value 0
R/W R/W
Description Arbitration Lost Flag/Overrun Error Flag This flag indicates that arbitration was lost in master mode with the I2C bus format and that the final bit has been received while RDRF = 1 with the clocked synchronous format. When two or more master devices attempt to seize the 2 bus at nearly the same time, if the I C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been taken by another master. [Setting conditions] * * * If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode When the SDA pin outputs high in master mode while a start condition is detected When the final bit is received with the clocked synchronous format while RDRF = 1 When 0 is written in AL/OVE after reading AL/OVE = 1
[Clearing condition] * 1 AAS 0 R/W Slave Address Recognition Flag In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting conditions] * * When the slave address is detected in slave receive mode When the general call address is detected in slave receive mode. When 0 is written in AAS after reading AAS = 1
[Clearing condition] * 0 ADZ 0 R/W General Call Address Recognition Flag This bit is valid in I2C bus format slave receive mode. [Setting condition] * When the general call address is detected in slave receive mode When 0 is written in ADZ after reading ADZ = 1
[Clearing condition] *
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Section 15 I C Bus Interface 2 (IIC2)
2
15.3.6
Slave Address Register (SAR)
SAR selects the communication format and sets the slave address. When the chip is in slave mode with the I2C bus format, if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device.
Bit 7 to 1 Bit Name SVA6 to SVA0 Initial Value All 0 R/W R/W Description Slave Address 6 to 0 These bits set a unique address in bits SVA6 to SVA0, differing form the addresses of other slave devices 2 connected to the I C bus. 0 R/W Format Select 0: I C bus format is selected. 1: Clocked synchronous serial format is selected.
2
0
FS
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Section 15 I C Bus Interface 2 (IIC2)
2
15.3.7
I2C Bus Transmit Data Register (ICDRT)
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible. If the MLS bit of ICMR is set to 1 and when the data is written to ICDRT, the MSB/LSB inverted data is read. The initial value of ICDRT is H'FF. The initial value of ICDRT is H'FF. 15.3.8 I2C Bus Receive Data Register (ICDRR)
ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a receive-only register, therefore the CPU cannot write to this register. The initial value of ICDRR is H'FF. 15.3.9 I2C Bus Shift Register (ICDRS)
ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the CPU.
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Section 15 I C Bus Interface 2 (IIC2)
2
15.4
Operation
The I2C bus interface can communicate either in I2C bus mode or clocked synchronous serial mode by setting FS in SAR. 15.4.1 I2C Bus Format
Figure 15.3 shows the I2C bus formats. Figure 15.4 shows the I2C bus timing. The first frame following a start condition always consists of 8 bits.
(a) I2C bus format (FS = 0)
S 1
SLA 7 1
R/W 1
A 1
DATA n
A 1
m
A/A
1
P
1
n: Transfer bit count (n = 1 to 8) m: Transfer frame count (m 1)
(b) I2C bus format (Start condition retransmission, FS = 0)
S 1 SLA 7 1 R/W 1 A 1 DATA n1
m1
A/A
S 1
SLA 7 1
R/W 1
A 1
DATA n2
m2
A/A
1
P
1
1
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8) m1 and m2: Transfer frame count (m1 and m2 1)
Figure 15.3 I2C Bus Formats
SDA
SCL S
1-7 SLA
8 R/W
9 A
1-7 DATA
8
9 A
1-7 DATA
8
9
A
P
Figure 15.4 I2C Bus Timing Legend S: SLA: Start condition. The master device drives SDA from high to low while SCL is high. Slave address
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Section 15 I C Bus Interface 2 (IIC2)
2
R/W:
Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receive device drives SDA to low. DATA: Transfer data P: Stop condition. The master device drives SDA from low to high while SCL is high. 15.4.2 Master Transmit Operation
In master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For master transmit mode operation timing, refer to figures 15.5 and 15.6. The transmission procedure and operations in master transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. Read the BBSY flag in ICCR2 to confirm that the bus is free. Set the MST and TRS bits in ICCR1 to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using MOV instruction. (Start condition issued) This generates the start condition. 3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data show the slave address and R/W) to ICDRT. At this time, TDRE is automatically cleared to 0, and data is transferred from ICDRT to ICDRS. TDRE is set again. 4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1 at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the slave device has been selected. Then, write second byte data to ICDRT. When ACKBR is 1, the slave device has not been acknowledged, so issue the stop condition. To issue the stop condition, write 0 to BBSY and SCP using MOV instruction. SCL is fixed low until the transmit data is prepared or the stop condition is issued. 5. The transmit data after the second byte is written to ICDRT every time TDRE is set. 6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or NACKF. 7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
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Section 15 I C Bus Interface 2 (IIC2)
2
SCL (Master output) SDA (Master output)
1 Bit 7
2 Bit 6
3 Bit 5
4 Bit 4
5 Bit 3
6 Bit 2
7 Bit 1
8 Bit 0
R/W
9
1 Bit 7
2 Bit 6
Slave address SDA (Slave output) TDRE
A
TEND
ICDRT
Address + R/W
Data 1
Data 2
ICDRS
Address + R/W
Data 1
User processing
[2] Instruction of start condition issuance
[4] Write data to ICDRT (second byte) [3] Write data to ICDRT (first byte) [5] Write data to ICDRT (third byte)
Figure 15.5 Master Transmit Mode Operation Timing (1)
SCL (Master output) SDA (Master output) SDA (Slave output)
9
1
Bit 7
2
Bit 6
3
Bit 5
4
Bit 4
5
Bit 3
6
Bit 2
7
Bit 1
8
Bit 0
9
A
A/A
TDRE
TEND
ICDRT
Data n
ICDRS
Data n
User [5] Write data to ICDRT processing
[6] Issue stop condition. Clear TEND. [7] Set slave receive mode
Figure 15.6 Master Transmit Mode Operation Timing (2)
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Section 15 I C Bus Interface 2 (IIC2)
2
15.4.3
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, refer to figures 15.7 and 15.8. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master transmit mode to master receive mode. Then, clear the TDRE bit to 0. 2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. The master device outputs the level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse. 3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF is cleared to 0. 4. The continuous reception is performed by reading ICDRR every time RDRF is set. If 8th receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is fixed low until ICDRR is read. 5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR. This enables the issuance of the stop condition after the next reception. 6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, issue the stage condition. 7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0. 8. The operation returns to the slave receive mode.
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Section 15 I C Bus Interface 2 (IIC2)
2
Master transmit mode SCL (Master output) SDA (Master output) SDA (Slave output)
Master receive mode
9
1
2
3
4
5
6
7
8
9 A
1
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
TDRE
TEND
TRS
RDRF
ICDRS
Data 1
ICDRR
User processing
Data 1
[3] Read ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read)
Figure 15.7 Master Receive Mode Operation Timing (1)
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Section 15 I C Bus Interface 2 (IIC2)
2
SCL (Master output) SDA (Master output) SDA (Slave output)
9 A
1
2
3
4
5
6
7
8
9 A/A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDRF
RCVD
ICDRS
Data n-1
Data n
ICDRR
User processing
Data n-1
Data n
[5] Read ICDRR after setting RCVD
[7] Read ICDRR, and clear RCVD
[6] Issue stop condition [8] Set slave receive mode
Figure 15.8 Master Receive Mode Operation Timing (2) 15.4.4 Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. For slave transmit mode operation timing, refer to figures 15.9 and 15.10. The transmission procedure and operations in slave transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS and ICSR bits in ICCR1 are set to 1, and the mode changes to slave transmit mode automatically. The continuous transmission is performed by writing transmit data to ICDRT every time TDRE is set. 3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1, with TDRE = 1. When TEND is set, clear TEND. 4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free. 5. Clear TDRE.
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Section 15 I C Bus Interface 2 (IIC2)
2
Slave receive mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output)
Slave transmit mode
9
1
2
3
4
5
6
7
8
9 A
1
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
TDRE
TEND
TRS
ICDRT
Data 1
Data 2
Data 3
ICDRS
Data 1
Data 2
ICDRR
User processing [2] Write data to ICDRT (data 1) [2] Write data to ICDRT (data 2) [2] Write data to ICDRT (data 3)
Figure 15.9 Slave Transmit Mode Operation Timing (1)
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Section 15 I C Bus Interface 2 (IIC2)
2
Slave receive mode Slave transmit mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output)
TDRE 9
A
1
2
3
4
5
6
7
8
9 A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TEND
TRS
ICDRT
ICDRS
Data n
ICDRR
User processing
[3] Clear TEND
[4] Read ICDRR (dummy read) after clearing TRS
[5] Clear TDRE
Figure 15.10 Slave Transmit Mode Operation Timing (2) 15.4.5 Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For slave receive mode operation timing, refer to figures 15.11 and 15.12. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the read data show the slave address and R/W, it is not used.)
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Section 15 I C Bus Interface 2 (IIC2)
2
3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be returned to the master device, is reflected to the next transmit frame. 4. The last byte data is read by reading ICDRR.
SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output)
9
1
2
3
4
5
6
7
8
9
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
A
A
RDRF
ICDRS
Data 1
Data 2
ICDRR
User processing
Data 1
[2] Read ICDRR (dummy read)
[2] Read ICDRR
Figure 15.11 Slave Receive Mode Operation Timing (1)
SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output)
9
1
Bit 7
2
Bit 6
3
Bit 5
4
Bit 4
5
Bit 3
6
Bit 2
7
Bit 1
8
Bit 0
9
A
A
RDRF
ICDRS
Data 1
Data 2
ICDRR
User processing
Data 1
[3] Set ACKBT
[3] Read ICDRR [4] Read ICDRR
Figure 15.12 Slave Receive Mode Operation Timing (2)
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Section 15 I C Bus Interface 2 (IIC2)
2
15.4.6
Clocked Synchronous Serial Format
This module can be operated with the clocked synchronous serial format, by setting the FS bit in SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When MST is 0, the external clock input is selected. Data Transfer Format Figure 15.13 shows the clocked synchronous serial transfer format. The transfer data is output from the rise to the fall of the SCL clock, and the data at the rising edge of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer, in either the MSB first or LSB first. The output level of SDA can be changed during the transfer wait, by the SDAO bit in ICCR2.
SCL
SDA
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5 Bit 6
Bit 7
Figure 15.13 Clocked Synchronous Serial Transfer Format Transmit Operation In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For transmit mode operation timing, refer to figure 15.14. The transmission procedure and operations in transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. Set the TRS bit in ICCR1 to select the transmit mode. Then, TDRE in ICSR is set. 3. Confirm that TDRE has been set. Then, write the transmit data to ICDRT. The data is transferred from ICDRT to ICDRS, and TDRE is set automatically. The continuous transmission is performed by writing data to ICDRT every time TDRE is set. When changing from transmit mode to receive mode, clear TRS while TDRE is 1.
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Section 15 I C Bus Interface 2 (IIC2)
2
SCL
SDA (Output)
1
2
7 Bit 6
8 Bit 7
1 Bit 0
7 Bit 6
8 Bit 7
1 Bit 0
Bit 0
Bit 1
TRS
TDRE
ICDRT ICDRS
Data 1 Data 1
Data 2 Data 2
Data 3 Data 3
User processing
[3] Write data [3] Write data to ICDRT to ICDRT [2] Set TRS
[3] Write data to ICDRT
[3] Write data to ICDRT
Figure 15.14 Transmit Mode Operation Timing Receive Operation In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to figure 15.15. The reception procedure and operations in receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. When the transfer clock is output, set MST to 1 to start outputting the receive clock. 3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is continually output. The continuous reception is performed by reading ICDRR every time RDRF is set. When the 8th clock is risen while RDRF is 1, the overrun is detected and AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR. 4. To stop receiving when MST = 1, set RCVD in ICCR1 to 1, then read ICDRR. Then, SCL is fixed high after receiving the next byte data.
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Section 15 I C Bus Interface 2 (IIC2)
2
SCL
SDA (Input)
1
2
7
Bit 6
8
Bit 7
1
Bit 0
7
Bit 6
8
Bit 7
1
2
Bit 0
Bit 0
Bit 1
MST TRS
RDRF ICDRS ICDRR
Data 1 Data 2 Data 3
Data 1 [2] Set MST (when outputting the clock)
Data 2
User processing
[3] Read ICDRR
[3] Read ICDRR
Figure 15.15 Receive Mode Operation Timing 15.4.7 Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 15.16 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
C SCL or SDA input signal D Latch Q
D
C Q Latch
March detector
Internal SCL or SDA signal
System clock period Sampling clock
Figure 15.16 Block Diagram of Noise Conceler
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Section 15 I C Bus Interface 2 (IIC2)
2
15.4.8
Example of Use
Flowcharts in respective modes that use the I2C bus interface are shown in figures 15.17 to 15.20.
Start Initialize Read BBSY in ICCR2 No [1] BBSY=0 ? Yes Set MST and TRS in ICCR1 to 1. Write 1 to BBSY and 0 to SCP. Write transmit data in ICDRT Read TEND in ICSR No [5] TEND=1 ? Yes Read ACKBR in ICIER [6] ACKBR=0 ? Yes Transmit mode? Yes No Mater receive mode No [11] Clear the TEND flag. [8] [9] Wait for ICDRT empty. Set the last byte of transmit data. [3] [2] [3] [4] [4] [5] [6] [7] Issue the start condition. Set the first byte (slave address + R/W) of transmit data. Wait for 1 byte to be transmitted. Test the acknowledge transferred from the specified slave device. Set the second and subsequent bytes (except for the final byte) of transmit data. [1] [2] Test the status of the SCL and SDA lines. Set master transmit mode.
[10] Wait for last byte to be transmitted.
Write transmit data in ICDRT Read TDRE in ICSR No
[7] [12] Clear STOP flag. [13] Issue the stop condition. [14] Wait for the creation of stop condition.
[8] TDRE=1 ? Yes
No
Last byte? [9]
[15] Set slave receive mode. Clear TDRE.
Yes Write transmit data in ICDRT Read TEND in ICSR No [10] TEND=1 ? Yes Clear TEND in ICSR Clear STOP in ISCR Write 0 to BBSY and SCP Read STOP in ICSR No [14] STOP=1 ? Yes Set MST to 1 and TRS to 0 in ICCR1 Clear TDRE in ICSR End [11] [12] [13]
[15]
Figure 15.17 Sample Flowchart for Master Transmit Mode
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Section 15 I C Bus Interface 2 (IIC2)
2
Mater receive mode
[1] Clear TEND, select master receive mode, and then clear TDRE.* Set acknowledge to the transmit device.* Dummy-read ICDDR.* Wait for 1 byte to be received Check whether it is the (last receive - 1). Read the receive data last. Set acknowledge of the final byte. Disable continuous reception (RCVD = 1). Read the (final byte - 1) of receive data. Wait for the last byte to be receive.
Clear TEND in ICSR Clear TRS in ICCR1 to 0 Clear TDRE in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR Read RDRF in ICSR
No
[2]
[2]
[1]
[3] [4] [5] [6] [7] [8]
[3]
RDRF=1 ?
Yes
[4]
Last receive - 1? No Read ICDRR
Yes
[5]
[9]
[10] Clear STOP flag.
[6]
[11] Issue the stop condition. [12] Wait for the creation of stop condition.
Set ACKBT in ICIER to 1
[7]
[13] Read the last byte of receive data. [14] Clear RCVD.
Set RCVD in ICCR1 to 1 Read ICDRR Read RDRF in ICSR
[8]
[15] Set slave receive mode.
No
RDRF=1 ?
Yes Clear STOP in ICSR
Write 0 to BBSY and SCP Read STOP in ICSR
[9]
[10]
[11]
No
[12]
STOP=1 ?
Yes
Read ICDRR Clear RCVD in ICCR1 to 0
[13]
[14]
Clear MST in ICCR1 to 0 End
[15]
Note: Do not activate an interrupt during the execution of steps [1] to [3].
Supplementary explanation: When one byte is received, steps [2] to [6] are skipped after step [1], before jumping to step [7]. The step [8] is dummy-read in ICDRR.
Figure 15.18 Sample Flowchart for Master Receive Mode
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Section 15 I C Bus Interface 2 (IIC2)
2
Slave transmit mode Clear AAS in ICSR Write transmit data in ICDRT Read TDRE in ICSR No [3] TDRE=1 ? Yes No
Last byte?
[1] Clear the AAS flag. [1] [2] Set transmit data for ICDRT (except for the last data). [3] Wait for ICDRT empty. [2] [4] Set the last byte of transmit data. [5] Wait for the last byte to be transmitted. [6] Clear the TEND flag . [7] Set slave receive mode. [8] Dummy-read ICDRR to release the SCL line. [4] [9] Clear the TDRE flag.
Yes Write transmit data in ICDRT Read TEND in ICSR No
[5] TEND=1 ? Yes Clear TEND in ICSR Clear TRS in ICCR1 to 0 Dummy read ICDRR Clear TDRE in ICSR End
[6] [7] [8] [9]
Figure 15.19 Sample Flowchart for Slave Transmit Mode
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Section 15 I C Bus Interface 2 (IIC2)
2
Slave receive mode
[1] Clear the AAS flag.
Clear AAS in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR
[1] [2] Set acknowledge to the transmit device. [2] [3] Dummy-read ICDRR. [3] [4] Wait for 1 byte to be received. [5] Check whether it is the (last receive - 1). [4] [6] Read the receive data. [7] Set acknowledge of the last byte.
Read RDRF in ICSR No RDRF=1 ? Yes
Last receive - 1?
Yes
[5]
[8] Read the (last byte - 1) of receive data. [9] Wait the last byte to be received.
No Read ICDRR
[6] [10] Read for the last byte of receive data.
Set ACKBT in ICIER to 1
[7]
Read ICDRR Read RDRF in ICSR No
[8]
[9]
RDRF=1 ? Yes Read ICDRR End
[10]
Supplementary explanation: When one byte is received, steps [2] to [6] are skipped after step [1], before jumping to step [7]. The step [8] is dummy-read in ICDRR.
Figure 15.20 Sample Flowchart for Slave Receive Mode
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Section 15 I C Bus Interface 2 (IIC2)
2
15.5
Interrupt Request
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost/overrun. Table 15.3 shows the contents of each interrupt request. Table 15.3 Interrupt Requests
Clocked Synchronous I2C Mode Mode
Interrupt Request Transmit Data Empty Transmit End Receive Data Full STOP Recognition NACK Receive Arbitration Lost/Overrun
Abbreviation TXI TEI RXI STPI NAKI
Interrupt Condition (TDRE = 1) * (TIE = 1) (TEND = 1) * (TEIE = 1) (RDRF = 1) * (RIE = 1) (STOP = 1) * (STIE = 1) {(NACKF = 1) + (AL = 1)} * (NAKIE = 1)
x x
When interrupt conditions described in table 15.3 are 1 and the I bit in CCR is 0, the CPU executes an interrupt exception processing. Interrupt sources should be cleared in the exception processing. TDRE and TEND are automatically cleared to 0 by writing the transmit data to ICDRT. RDRF are automatically cleared to 0 by reading ICDRR. TDRE is set to 1 again at the same time when transmit data is written to ICDRT. When TDRE is cleared to 0, then an excessive data of one byte may be transmitted.
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Section 15 I C Bus Interface 2 (IIC2)
2
15.6
Bit Synchronous Circuit
In master mode,this module has a possibility that high level period may be short in the two states described below. * When SCL is driven to low by the slave device * When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 15.21 shows the timing of the bit synchronous circuit and table 15.4 shows the time when SCL output changes from low to Hi-Z then SCL is monitored.
SCL monitor timing reference clock
SCL
VIH
Internal SCL
Figure 15.21 The Timing of the Bit Synchronous Circuit Table 15.4 Time for Monitoring SCL
CKS3 0 CKS2 0 1 1 0 1 Time for Monitoring SCL 7.5 tcyc 19.5 tcyc 17.5 tcyc 41.5 tcyc
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Section 15 I C Bus Interface 2 (IIC2)
2
15.7
15.7.1
Usage Notes
Issue (Retransmission) of Start/Stop Conditions
In master mode, when the start/stop conditions are issued (retransmitted) at the specific timing under the following condition 1 or 2, such conditions may not be output successfully. To avoid this, issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. Check the SCLO bit in the I2C control register 2 (IICR2) to confirm the fall of the ninth clock. 1. When the rising of SCL falls behind the time specified in section 17.6, Bit Synchronous Circuit, by the load of the SCL bus (load capacitance or pull-up resistance) 2. When the bit synchronous circuit is activated by extending the low period of eighth and ninth clocks, that is driven by the slave device 15.7.2 WAIT Setting in I2C Bus Mode Register (ICMR)
If the WAIT bit is set to 1, and the SCL signal is driven low for two or more transfer clocks by the slave device at the eighth and ninth clocks, the high period of ninth clock may be shortened. To avoid this, set the WAIT bit in ICMR to 0.
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Section 16 A/D Converter
Section 16 A/D Converter
This LSI includes a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. The block diagram of the A/D converter is shown in figure 16.1.
16.1
* * * *
Features
* * *
*
10-bit resolution Eight input channels Conversion time: at least 3.5 s per channel (at 20-MHz operation) Two operating modes Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels Four data registers Conversion results are held in a data register for each channel Sample-and-hold function Two conversion start methods Software External trigger signal Interrupt request An A/D conversion end interrupt request (ADI) can be generated
ADCMS32A_000020020200
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Section 16 A/D Converter
Module data bus
Internal data bus
AVCC
Successive approximations register
10-bit D/A
A D D R A
A D D R B
A D D R C
A D D R D
A D C S R
A D C R
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Analog multiplexer
+ Control circuit Comparator Sample-andhold circuit
Bus interface
/4 /8
ADI interrupt
ADTRG
[Legend] ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD:
A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D
Figure 16.1 Block Diagram of A/D Converter
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Section 16 A/D Converter
16.2
Input/Output Pins
Table 16.1 summarizes the input pins used by the A/D converter. The 8 analog input pins are divided into two groups; analog input pins 0 to 3 (AN0 to AN3) comprising group 0, analog input pins 4 to 7 (AN4 to AN7) comprising group 1. The AVcc pin is the power supply pin for the analog block in the A/D converter. Table 16.1 Pin Configuration
Pin Name Analog power supply pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin Abbreviation AVCC AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG I/O Input Input Input Input Input Input Input Input Input Input External trigger input for starting A/D conversion Group 1 analog input Function Analog block power supply Group 0 analog input
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Section 16 A/D Converter
16.3
Register Descriptions
The A/D converter has the following registers. * * * * * * A/D data register A (ADDRA) A/D data register B (ADDRB) A/D data register C (ADDRC) A/D data register D (ADDRD) A/D control/status register (ADCSR) A/D control register (ADCR) A/D Data Registers A to D (ADDRA to ADDRD)
16.3.1
There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each analog input channel, are shown in table 16.2. The converted 10-bit data is stored in bits 15 to 6. The lower 6 bits are always read as 0. The data bus width between the CPU and the A/D converter is 8 bits. The upper byte can be read directly from the CPU, however the lower byte should be read via a temporary register. The temporary register contents are transferred from the ADDR when the upper byte data is read. Therefore byte access to ADDR should be done by reading the upper byte first then the lower one. Word access is also possible. ADDR is initialized to H'0000. Table 16.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register to Be Stored Results of A/D Conversion ADDRA ADDRB ADDRC ADDRD
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Section 16 A/D Converter
16.3.2
A/D Control/Status Register (ADCSR)
ADCSR consists of the control bits and conversion end status bits of the A/D converter.
Bit 7 Bit Name ADF Initial Value 0 R/W R/W Description A/D End Flag [Setting conditions] * * When A/D conversion ends in single mode When A/D conversion ends once on all the channels selected in scan mode When 0 is written after reading ADF = 1
[Clearing condition] * 6 ADIE 0 R/W A/D Interrupt Enable A/D conversion end interrupt request (ADI) is enabled by ADF when this bit is set to 1 5 ADST 0 R/W A/D Start Setting this bit to 1 starts A/D conversion. In single mode, this bit is cleared to 0 automatically when conversion on the specified channel is complete. In scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to standby mode. 4 SCAN 0 R/W Scan Mode Selects single mode or scan mode as the A/D conversion operating mode. 0: Single mode 1: Scan mode 3 CKS 0 R/W Clock Select Selects the A/D conversions time. 0: Conversion time = 134 states (max.) 1: Conversion time = 70 states (max.) Clear the ADST bit to 0 before switching the conversion time.
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Section 16 A/D Converter
Bit 2 1 0
Bit Name CH2 CH1 CH0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Channel Select 2 to 0 Select analog input channels. When SCAN = 0 000: AN0 001: AN1 010: AN2 011: AN3 100: AN4 101: AN5 110: AN6 111: AN7 When SCAN = 1 000: AN0 001: AN0 and AN1 010: AN0 to AN2 011: AN0 to AN3 100: AN4 101: AN4 and AN5 110: AN4 to AN6 111: AN4 to AN7
16.3.3
A/D Control Register (ADCR)
ADCR enables A/D conversion started by an external trigger signal.
Bit 7 Bit Name TRGE Initial Value 0 R/W R/W Description Trigger Enable A/D conversion is started at the falling edge and the rising edge of the external trigger signal (ADTRG) when this bit is set to 1. The selection between the falling edge and rising edge of the external trigger pin (ADTRG) conforms to the WPEG5 bit in the interrupt edge select register 2 (IEGR2) 6 to 1 0 -- -- All 1 0 -- R/W Reserved These bits are always read as 1. Reserved Do not set this bit to 1, though the bit is readable/writable.
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Section 16 A/D Converter
16.4
Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST in ADCSR to 0. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 16.4.1 Single Mode
In single mode, A/D conversion is performed once for the analog input of the specified single channel as follows: 1. A/D conversion is started when the ADST bit in ADCSR is set to 1, according to software or external trigger input. 2. When A/D conversion is completed, the result is transferred to the corresponding A/D data register of the channel. 3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters the wait state. 16.4.2 Scan Mode
In scan mode, A/D conversion is performed sequentially for the analog input of the specified channels (four channels maximum) as follows: 1. When the ADST bit in ADCSR is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1). 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF flag in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt requested is generated. A/D conversion starts again on the first channel in the group. 4. The ADST bit is not automatically cleared to 0. Steps [2] and [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops.
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Section 16 A/D Converter
16.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then starts conversion. Figure 16.2 shows the A/D conversion timing. Table 16.3 shows the A/D conversion time. As indicated in figure 16.2, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 16.3. In scan mode, the values given in table 16.3 apply to the first conversion time. In the second and subsequent conversions, the conversion time is 128 states (fixed) when CKS = 0 and 66 states (fixed) when CKS = 1.
(1) Address (2)
Write signal Input sampling timing
ADF tD tSPL tCONV [Legend] ADCSR write cycle (1) : ADCSR address (2) : A/D conversion start delay time tD : tSPL : Input sampling time tCONV : A/D conversion time
Figure 16.2 A/D Conversion Timing
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Section 16 A/D Converter
Table 16.3 A/D Conversion Time (Single Mode)
CKS = 0 Item A/D conversion start delay time Input sampling time A/D conversion time Symbol tD tSPL tCONV Min 6 -- 131 Typ -- 31 -- Max 9 -- 134 Min 4 -- 69 CKS = 1 Typ -- 15 -- Max 5 -- 70
Note: All values represent the number of states.
16.4.4
External Trigger Input Timing
A/D conversion can also be started by an external trigger input. When the TRGE bit in ADCR is set to 1, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG input pin sets the ADST bit in ADCSR to 1, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 16.3 shows the timing.
ADTRG
Internal trigger signal
ADST A/D conversion
Figure 16.3 External Trigger Input Timing
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Section 16 A/D Converter
16.5
A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.4). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 16.5). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from 1111111110 to 1111111111 (see figure 16.5). * Nonlinearity error The deviation from the ideal A/D conversion characteristic as the voltage changes from zero to full scale. This does not include the offset error, full-scale error, or quantization error. * Absolute accuracy The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error.
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Section 16 A/D Converter
Digital output
111 110 101 100 011 010 001 000 1 8
Ideal A/D conversion characteristic
Quantization error
2 8
3 8
4 8
5 8
6 8
7 FS 8 Analog input voltage
Figure 16.4 A/D Conversion Accuracy Definitions (1)
Full-scale error
Digital output
Ideal A/D conversion characteristic
Nonlinearity error Actual A/D conversion characteristic FS Analog input voltage
Offset error
Figure 16.5 A/D Conversion Accuracy Definitions (2)
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Section 16 A/D Converter
16.6
16.6.1
Usage Notes
Permissible Signal Source Impedance
This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k, charging may be insufficient and it may not be possible to guarantee A/D conversion accuracy. However, for A/D conversion in single mode with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 16.6). When converting a high-speed analog signal or converting in scan mode, a low-impedance buffer should be inserted. 16.6.2 Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND. Care is also required to ensure that filter circuits do not interfere with digital signals or act as antennas on the mounting board.
This LSI Sensor output impedance up to 5 k Sensor input Low-pass filter C to 0.1 F Cin = 15 pF
A/D converter equivalent circuit
10 k 20 pF
Figure 16.6 Analog Input Circuit Example
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Section 17 EEPROM
Section 17 EEPROM
The H8/3694N has an on-chip 512-byte EEPROM. The block diagram of the EEPROM is shown in figure 17.1.
17.1
Features
* Two writing methods: 1-byte write Page write: Page size 8 bytes * Three reading methods: Current address read Random address read Sequential read * Acknowledge polling possible * Write cycle time: 10 ms (power supply voltage Vcc = 2.7 V or more) * Write/Erase endurance: 104 cycles/byte (byte write mode), 105 cycles/page (page write mode) * Data retention: 10 years after the write cycle of 104 cycles (page write mode) * Interface with the CPU I2C bus interface (complies with the standard of Philips Corporation) Device code 1010 Sleep address code can be changed (initial value: 000) The I2C bus is open to the outside, so the EEPROM can be directly accessed from the outside.
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Section 17 EEPROM
EEPROM Data bus
H'FF10
Y decoder
EEPROM Key register (EKR)
Address bus
Y-select/ Sense amp.
Key control circuit
Memory array User area (512 bytes)
X decoder
H'0000 H'01FF
SDA
SCL
I2C bus interface control circuit
Slave address register
H'FF09
ESAR
Power-on reset
Booster circuit EEPROM module
[Legend] ESAR: Register for referring the slave address (specifies the slave address of the memory array)
Figure 17.1 Block Diagram of EEPROM
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Section 17 EEPROM
17.2
Input/Output Pins
Pins used in the EEPROM are listed in table 17.1. Table 17.1 Pin Configuration
Pin name Serial clock pin Symbol SCL Input/Output Input Function The SCL pin is used to control serial input/output data timing. The data is input at the rising edge of the clock and output at the falling edge of the clock. The SCL pin needs to be pulled up by resistor as that 2 pin is open-drain driven structure of the I C pin. Use proper resistor value for your system by considering VOL, IOL, and the CIN pin capacitance in section 21.2.2, DC Characteristics and in section 21.2.3, AC Characteristics. Maximum clock frequency is 400 kHz. The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that pin is open-drain driven structure. Use proper resistor value for your system by considering VOL, IOL, and the CIN pin capacitance in section 21.2.2, DC Characteristics and in section 21.2.3, AC Characteristics. Except for a start condition and a stop condition which will be discussed later, the highto-low and low-to-high change of SDA input should be done during SCL low periods.
Serial data pin
SDA
Input/Output
17.3
Register Description
The EEPROM has a following register. * EEPROM key register (EKR) 17.3.1 EEPROM Key Register (EKR)
EKR is an 8-bit readable/writable register, which changes the slave address code written in the EEPROM. The slave address code is changed by writing H'5F in EKR and then writing either of H'00 to H'07 as an address code to the H'FF09 address in the EEPROM by the byte write method. EKR is initialized to H'FF.
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Section 17 EEPROM
17.4
17.4.1
Operation
EEPROM Interface
The HD64N3694G has a multi-chip structure with two internal chips of the HD64F3694G (FZTATTM version) and 512-byte EEPROM. The HD6483694G has a multi-chip structure with two internal chips of the HD6433694G (mask-ROM version) and 512-byte EEPROM. The EEPROM interface is the I2C bus interface. This I2C bus is open to the outside, so the communication with the external devices connected to the I2C bus can be made. 17.4.2 Bus Format and Timing
The I2C bus format and the I2C bus timing follow section 15.4.1, I2C Bus Format. The bus formats specific for the EEPROM are the following two. 1. The EEPROM address is configured of two bytes, the write data is transferred in the order of upper address and lower address from each MSB side. 2. The write data is transmitted from the MSB side. The bus format and bus timing of the EEPROM are shown in figure 17.2.
Start condition Slave address R/W ACK Upper memory lower memory ACK ACK address address Data ACK Data Stop conditon ACK
SCL
1
2
3
4
5
6
7
8
9
1
8
9
1
8
9
1
8
9
1
8
9
SDA [Legend] R/W: R/W code (0 is for a write and 1 is for a read), ACK: acknowledge
A15
A8
A7
A0
D7
D0
D7
D0
Figure 17.2 EEPROM Bus Format and Bus Timing 17.4.3 Start Condition
A high-to-low transition of the SDA input with the SCL input high is needed to generate the start condition for starting read, write operation.
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Section 17 EEPROM
17.4.4
Stop Condition
A low-to-high transition of the SDA input with the SCL input high is needed to generate the stop condition for stopping read, write operation. The standby operation starts after a read sequence by a stop condition. In the case of write operation, a stop condition terminates the write data inputs and place the device in an internallytimed write cycle to the memories. After the internally-timed write cycle (tWC) which is specified as tWC, the device enters a standby mode. 17.4.5 Acknowledge
All address data and serial data such as read data and write data are transmitted to and from in 8bit unit. The acknowledgement is the signal that indicates that this 8-bit data is normally transmitted to and from. In the write operation, EEPROM sends "0" to acknowledge in the ninth cycle after receiving the data. In the read operation, EEPROM sends a read data following the acknowledgement after receiving the data. After sending read data, the EEPROM enters the bus open state. If the EEPROM receives "0" as an acknowledgement, it sends read data of the next address. If the EEPROM does not receive acknowledgement "0" and receives a following stop condition, it stops the read operation and enters a standby mode. If the EEPROM receives neither acknowledgement "0" nor a stop condition, the EEPROM keeps bus open without sending read data. 17.4.6 Slave Addressing
The EEPROM device receives a 7-bit slave address and a 1-bit R/W code following the generation of the start conditions. The EEPROM enables the chip for a read or a write operation with this operation. The slave address consists of a former 4-bit device code and latter 3-bit slave address as shown in table 17.2. The device code is used to distinguish device type and this LSI uses "1010" fixed code in the same manner as in a general-purpose EEPROM. The slave address code selects one device out of all devices with device code 1010 (8 devices in maximum) which are connected to the I2C bus. This means that the device is selected if the inputted slave address code received in the order of A2, A1, A0 is equal to the corresponding slave address reference register (ESAR). The slave address code is stored in the address H'FF09 in the EEPROM. It is transferred to ESAR from the slave address register in the memory array during 10 ms after the reset is released. An access to the EEPROM is not allowed during transfer.
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Section 17 EEPROM
The initial value of the slave address code written in the EEPROM is H'00. It can be written in the range of H'00 to H'07. Be sure to write the data by the byte write method. The next one bit of the slave address is the R/W code. 0 is for a write and 1 is for a read. The EEPROM turns to a standby state if the device code is not "1010" or slave address code doesn't coincide. Table 17.2 Slave Addresses
Bit 7 6 5 4 3 2 1 Bit name Device code D3 Device code D2 Device code D1 Device code D0 Initial Value Setting Value 1 0 1 0 A2 A1 A0 The initial value can be changed The initial value can be changed The initial value can be changed Remarks
Slave address code A2 0 Slave address code A1 0 Slave address code A0 0
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Section 17 EEPROM
17.4.7
Write Operations
There are two types write operations; byte write operation and page write operation. To initiate the write operation, input 0 to R/W code following the slave address. 1. Byte Write A write operation requires an 8-bit data of a 7-bit slave address with R/W code = "0". Then the EEPROM sends acknowledgement "0" at the ninth bit. This enters the write mode. Then, two bytes of the memory address are received from the MSB side in the order of upper and lower. Upon receipt of one-byte memory address, the EEPROM sends acknowledgement "0" and receives a following a one-byte write data. After receipt of write data, the EEPROM sends acknowledgement "0". If the EEPROM receives a stop condition, the EEPROM enters an internally controlled write cycle and terminates receipt of SCL and SDA inputs until completion of the write cycle. The EEPROM returns to a standby mode after completion of the write cycle. The byte write operation is shown in figure 17.3.
SCL
1
2
3
4
5
6
7
8
9
1
8
9
1
8
9
1
8
9
SDA
A15
A8
A7
A0
D7
D0
Slave address Start condition [Legend] R/W: R/W code (0 is for a write and 1 is for a read) ACK: acknowledge
R/W ACK
Upper memory address
ACK
lower memory address
ACK
Write Data
ACK
Stop conditon
Figure 17.3 Byte Write Operation 2. Page Write This LSI is capable of the page write operation which allows any number of bytes up to 8 bytes to be written in a single write cycle. The write data is input in the same sequence as the byte write in the order of a start condition, slave address + R/W code, memory address (n), and write data (Dn) with every ninth bit acknowledgement "0" output. The EEPROM enters the page write operation if the EEPROM receives more write data (Dn+1) is input instead of receiving a stop condition after receiving the write data (Dn). LSB 3 bits (A2 to A0) in the EEPROM address are automatically incremented to be the (n+1) address upon receiving write data (Dn+1). Thus the write data can be received sequentially.
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Section 17 EEPROM
Addresses in the page are incremented at each receipt of the write data and the write data can be input up to 8 bytes. If the LSB 3 bits (A2 to A0) in the EEPROM address reach the last address of the page, the address will roll over to the first address of the same page. When the address is rolled over, write data is received twice or more to the same address, however, the last received data is valid. At the receipt of the stop condition, write data reception is terminated and the write operation is entered. The page write operation is shown in figure 17.4.
SCL
1
2
3
4
5
6
7
8
9
1
8
9
1
8
9
1
8
9
SDA
A15
A8
A7
A0
D7
D0
D7
D0
Slave address Start condition
R/W ACK
Upper memory lower memory ACK ACK Write Data address address
ACK
Write Data ACK Stop conditon
[Legend] R/W: R/W code (0 is for a write and 1 is for a read), ACK: acknowledge
Figure 17.4 Page Write Operation 17.4.8 Acknowledge Polling
Acknowledge polling feature is used to show if the EEPROM is in an internally-timed write cycle or not. This feature is initiated by the input of the 8-bit slave address + R/W code following the start condition during an internally-timed write cycle. Acknowledge polling will operate R/W code = "0". The ninth acknowledgement judges if the EEPROM is an internally-timed write cycle or not. Acknowledgement "1" shows the EEPROM is in a internally-timed write cycle and acknowledgement "0" shows the internally-timed write cycle has been completed. The acknowledge polling starts to function after a write data is input, i.e., when the stop condition is input.
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Section 17 EEPROM
17.4.9
Read Operation
There are three read operations; current address read, random address read, and sequential read. Read operations are initiated in the same way as write operations with the exception of R/W = 1. 1. Current Address Read The internal address counter maintains the (n+1) address that is made by the last address (n) accessed during the last read or write operation, with incremented by one. Current address read accesses the (n+1) address kept by the internal address counter. After receiving in the order of a start condition and the slave address + R/W code (R/W = 1), the EEPROM outputs the 1-byte data of the (n+1) address from the most significant bit following acknowledgement "0". If the EEPROM receives in the order of acknowledgement "1" and a following stop condition, the EEPROM stops the read operation and is turned to a standby state. In case the EEPROM has accessed the last address H'01FF at previous read operation, the current address will roll over and returns to zero address. In case the EEPROM has accessed the last address of the page at previous write operation, the current address will roll over within page addressing and returns to the first address in the same page. The current address is valid while power is on. The current address after power on will be undefined. After power is turned on, define the address by the random address read operation described below is necessary. The current address read operation is shown in figure 17.5.
SCL
1
2
3
4
5
6
7
8
9
1
8
9
SDA
D7
D0
Slave address Start condition [Legend] R/W: R/W code (0 is for a write and 1 is for a read) ACK: acknowledge
R/W ACK
Read Data
ACK
Stop conditon
Figure 17.5 Current Address Read Operation
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Section 17 EEPROM
2. Random Address Read This is a read operation with defined read address. A random address read requires a dummy write to set read address. The EEPROM receives a start condition, slave address + R/W code (R/W = 0), memory address (upper) and memory address (lower) sequentially. The EEPROM outputs acknowledgement "0" after receiving memory address (lower) then enters a current address read with receiving a start condition again. The EEPROM outputs the read data of the address which was defined in the dummy write operation. After receiving acknowledgement "1" and a following stop condition, the EEPROM stops the random read operation and returns to a standby state. The random address read operation is shown in figure 17.6.
SCL
1
2
3
4
5
6
7
8
9
1
8
9
1
8
9
1
2
3
4
5
6
7
8
9
1
8
9
SDA
A15
A8
A7
A0
D7
D0
Slave address Start condition [Legend]
R/W ACK
Upper memory lower memory ACK ACK address address
Slave address Start condition
R ACK
Read Data
ACK
Stop conditon
R/W: R/W code (0 is for a write and 1 is for a read), ACK: acknowledge
Figure 17.6 Random Address Read Operation 3. Sequential Read This is a mode to read the data sequentially. Data is sequential read by either a current address read or a random address read. If the EEPROM receives acknowledgement "0" after 1-byte read data is output, the read address is incremented and the next 1-byte read data are coming out. Data is output sequentially by incrementing addresses as long as the EEPROM receives acknowledgement "0" after the data is output. The address will roll over and returns address zero if it reaches the last address H'01FF. The sequential read can be continued after roll over. The sequential read is terminated if the EEPROM receives acknowledgement "1" and a following stop condition as the same manner as in the random address read. The condition of a sequential read when the current address read is used is shown in figure 17.7.
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Section 17 EEPROM
SCL
1
2
3
4
5
6
7
8
9
1
8
9
1
8
9
SDA
D7
D0
D7
D0
Slave address Start condition
R/W ACK
Read Data ACK
****
Read Data
ACK Stop conditon
[Legend] R/W: R/W code (0 is for a write and 1 is for a read) ACK: acknowledge
Figure 17.7 Sequential Read Operation (when current address read is used)
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Section 17 EEPROM
17.5
17.5.1
Usage Notes
Data Protection at VCC On/Off
When VCC is turned on or off, the data might be destroyed by malfunction. Be careful of the notices described below to prevent the data to be destroyed. 1. SCL and SDA should be fixed to VCC or VSS during VCC on/off. 2. VCC should be turned off after the EEPROM is placed in a standby state. 3. When VCC is turned on from the intermediate level, malfunction is caused, so VCC should be turned on from the ground level (VSS). 4. VCC turn on speed should be longer than 10 us. 17.5.2 Write/Erase Endurance
The endurance is 105 cycles/page (1% cumulative failure rate) in case of page programming and 104 cycles/byte in case of byte programming. The data retention time is more than 10 years when a device is page-programmed less than 104 cycles. 17.5.3 Noise Suppression Time
This EEPROM has a noise suppression function at SCL and SDA inputs, that cuts noise of width less than 50 ns. Be careful not to allow noise of width more than 50 ns because the noise of with more than 50 ms is recognized as an active pulse.
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Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
This LSI can include a power-on reset circuit and low-voltage detection circuit as optional circuits. The low-voltage detection circuit consists of two circuits: LVDI (interrupt by low voltage detect) and LVDR (reset by low voltage detect) circuits. This circuit is used to prevent abnormal operation (runaway execution) from occurring due to the power supply voltage fall and to recreate the state before the power supply voltage fall when the power supply voltage rises again. Even if the power supply voltage falls, the unstable state when the power supply voltage falls below the guaranteed operating voltage can be removed by entering standby mode when exceeding the guaranteed operating voltage and during normal operation. Thus, system stability can be improved. If the power supply voltage falls more, the reset state is automatically entered. If the power supply voltage rises again, the reset state is held for a specified period, then active mode is automatically entered. Figure 18.1 is a block diagram of the power-on reset circuit and the low-voltage detection circuit.
18.1
Features
* Power-on reset circuit Uses an external capacitor to generate an internal reset signal when power is first supplied. * Low-voltage detection circuit LVDR: Monitors the power-supply voltage, and generates an internal reset signal when the voltage falls below a specified value. LVDI: Monitors the power-supply voltage, and generates an interrupt when the voltage falls below or rises above respective specified values. Two pairs of detection levels for reset generation voltage are available: when only the LVDR circuit is used, or when the LVDI and LVDR circuits are both used.
LVI0000A_000020030300
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Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
CK R
OVF PSS R
RES
Noise canceler
Q S Power-on reset circuit
Internal reset signal
CRES
Noise canceler
Vreset Vcc Ladder resistor Vint
+ - + - LVDINT LVDRES Interrupt control circuit LVDSR
Reference voltage generator
Interrupt request Low-voltage detection circuit
[Legend] PSS: LVDCR: LVDSR: LVDRES: LVDINT: Vreset: Vint: Prescaler S Low-voltage-detection control register Low-voltage-detection status register Low-voltage-detection reset signal Low-voltage-detection interrupt signal Reset detection voltage Power-supply fall/rise detection voltage
Figure 18.1 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit
18.2
Register Descriptions
The low-voltage detection circuit has the following registers. * Low-voltage-detection control register (LVDCR) * Low-voltage-detection status register (LVDSR) 18.2.1 Low-Voltage-Detection Control Register (LVDCR)
LVDCR is used to enable or disable the low-voltage detection circuit, set the detection levels for the LVDR function, enable or disable the LVDR function, and enable or disable generation of an interrupt when the power-supply voltage rises above or falls below the respective levels.
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Internal data bus
LVDCR
Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Table 18.1 shows the relationship between the LVDCR settings and select functions. LVDCR should be set according to table 18.1.
Bit 7 Bit Name LVDE Initial Value 0* R/W R/W Description LVD Enable 0: The low-voltage detection circuit is not used (In standby mode) 1: The low-voltage detection circuit is used 6 to 4 3 LVDSEL All 1 0* R/W Reserved These bits are always read as 1, and cannot be modified. LVDR Detection Level Select 0: Reset detection voltage is 2.3 V (typ.) 1: Reset detection voltage is 3.6 V (typ.) When the falling or rising voltage detection interrupt is used, reset detection voltage of 2.3 V (typ.) should be used. When only a reset detection interrupt is used, reset detection voltage of 3.6 V (typ.) should be used. 2 LVDRE 0* R/W LVDR Enable 0: Disables the LVDR function 1: Enables the LVDR function 1 LVDDE 0 R/W Voltage-Fall-Interrupt Enable 0: Interrupt on the power-supply voltage falling below the selected detection level disabled 1: Interrupt on the power-supply voltage falling below the selected detection level enabled 0 LVDUE 0 R/W Voltage-Rise-Interrupt Enable 0: Interrupt on the power-supply voltage rising above the selected detection level disabled 1: Interrupt on the power-supply voltage rising above the selected detection level enabled Note: * Not initialized by LVDR but initialized by a power-on reset or WDT reset.
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Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Table 18.1 LVDCR Settings and Select Functions
LVDCR Settings Select Functions
Low-VoltageDetection Falling Interrupt Low-VoltageDetection Rising Interrupt
LVDE
LVDSEL
LVDRE
LVDDE
LVDUE
Power-On Reset
LVDR
0 1 1 1 1 Legend:
* 1 0 0 0
* 1 0 0 1 *: means invalid.
* 0 1 1 1
* 0 0 1 1
O O O O O
O O
O O O
O O
18.2.2
Low-Voltage-Detection Status Register (LVDSR)
LVDSR indicates whether the power-supply voltage falls below or rises above the respective specified values.
Bit 7 to 2 1 Bit Name LVDDF Initial Value All 1 0* R/W R/W Description Reserved These bits are always read as 1, and cannot be modified. LVD Power-Supply Voltage Fall Flag [Setting condition] When the power-supply voltage falls below Vint (D) (typ. = 3.7 V) [Clearing condition] Writing 0 to this bit after reading it as 1 0 LVDUF 0* R/W LVD Power-Supply Voltage Rise Flag [Setting condition] When the power supply voltage falls below Vint (D) while the LVDUE bit in LVDCR is set to 1, then rises above Vint (U) (typ. = 4.0 V) before falling below Vreset1 (typ. = 2.3 V) [Clearing condition] Writing 0 to this bit after reading it as 1 Note: * Initialized by LVDR.
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Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
18.3
18.3.1
Operation
Power-On Reset Circuit
Figure 18.2 shows the timing of the operation of the power-on reset circuit. As the power-supply voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via the on-chip pull-up resistor (typ. 150 k). Since the state of the RES pin is transmitted within the chip, the prescaler S and the entire chip are in their reset states. When the level on the RES pin reaches the specified value, the prescaler S is released from its reset state and it starts counting. The OVF signal is generated to release the internal reset signal after the prescaler S has counted 131,072 clock () cycles. The noise cancellation circuit of approximately 100 ns is incorporated to prevent the incorrect operation of the chip by noise on the RES pin. To achieve stable operation of this LSI, the power supply needs to rise to its full level and settles within the specified time. The maximum time required for the power supply to rise and settle after power has been supplied (tPWON) is determined by the oscillation frequency (fOSC) and capacitance which is connected to RES pin (CRES). If tPWON means the time required to reach 90 % of power supply voltage, the power supply circuit should be designed to satisfy the following formula.
tPWON (ms) 90 x CRES (F) + 162/fOSC (MHz) (tPWON 3000 ms, CRES 0.22 F, and fOSC = 10 in 2-MHz to 10-MHz operation)
Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV and rise after charge on the RES pin is removed. To remove charge on the RES pin, it is recommended that the diode should be placed near Vcc. If the power supply voltage (Vcc) rises from the point above Vpor, a power-on reset may not occur.
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Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
tPWON Vcc
Vpor
Vss RES Vss PSS-reset signal OVF Internal reset signal
131,072 cycles PSS counter starts Reset released
Figure 18.2 Operational Timing of Power-On Reset Circuit 18.3.2 Low-Voltage Detection Circuit
LVDR (Reset by Low Voltage Detect) Circuit: Figure 18.3 shows the timing of the LVDR function. The LVDR enters the module-standby state after a power-on reset is canceled. To operate the LVDR, set the LVDE bit in LVDCR to 1, wait for 50 s (tLVDON) until the reference voltage and the low-voltage-detection power supply have stabilized by a software timer, etc., then set the LVDRE bit in LVDCR to 1. After that, the output settings of ports must be made. To cancel the low-voltage detection circuit, first the LVDRE bit should be cleared to 0 and then the LVDE bit should be cleared to 0. The LVDE and LVDRE bits must not be cleared to 0 simultaneously because incorrect operation may occur. When the power-supply voltage falls below the Vreset voltage (typ. = 2.3 V or 3.6 V), the LVDR clears the LVDRES signal to 0, and resets the prescaler S. The low-voltage detection reset state remains in place until a power-on reset is generated. When the power-supply voltage rises above the Vreset voltage again, the prescaler S starts counting. It counts 131,072 clock () cycles, and then releases the internal reset signal. In this case, the LVDE, LVDSEL, and LVDRE bits in LVDCR are not initialized. Note that if the power supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises from that point, the low-voltage detection reset may not occur. If the power supply voltage (Vcc) falls below Vpor = 100 mV, a power-on reset occurs.
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Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
VCC
Vreset
VLVDRmin VSS LVDRES
PSS-reset signal
OVF
Internal reset signal
131,072 cycles
PSS counter starts
Reset released
Figure 18.3 Operational Timing of LVDR Circuit LVDI (Interrupt by Low Voltage Detect) Circuit: Figure 18.4 shows the timing of LVDI functions. The LVDI enters the module-standby state after a power-on reset is canceled. To operate the LVDI, set the LVDE bit in LVDCR to 1, wait for 50 s (tLVDON) until the reference voltage and the low-voltage-detection power supply have stabilized by a software timer, etc., then set the LVDDE and LVDUE bits in LVDCR to 1. After that, the output settings of ports must be made. To cancel the low-voltage detection circuit, first the LVDDE and LVDUE bits should all be cleared to 0 and then the LVDE bit should be cleared to 0. The LVDE bit must not be cleared to 0 at the same timing as the LVDDE and LVDUE bits because incorrect operation may occur. When the power-supply voltage falls below Vint (D) (typ. = 3.7 V) voltage, the LVDI clears the LVDINT signal to 0 and the LVDDF bit in LVDSR is set to 1. If the LVDDE bit is 1 at this time, an IRQ0 interrupt request is simultaneously generated. In this case, the necessary data must be saved in the external EEPROM, etc, and a transition must be made to standby mode or subsleep mode. Until this processing is completed, the power supply voltage must be higher than the lower limit of the guaranteed operating voltage. When the power-supply voltage does not fall below Vreset1 (typ. = 2.3 V) voltage but rises above Vint (U) (typ. = 4.0 V) voltage, the LVDI sets the LVDINT signal to 1. If the LVDUE bit is 1 at
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Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
this time, the LVDUF bit in LVDSR is set to 1 and an IRQ0 interrupt request is simultaneously generated. If the power supply voltage (Vcc) falls below Vreset1 (typ. = 2.3 V) voltage, the LVDR function is performed.
Vcc
Vint (U) Vint (D)
Vreset1
VSS LVDINT
LVDDE
LVDDF
LVDUE LVDUF
IRQ0 interrupt generated IRQ0 interrupt generated
Figure 18.4 Operational Timing of LVDI Circuit
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Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Procedures for Clearing Settings when Using LVDR and LVDI: To operate or release the low-voltage detection circuit normally, follow the procedure described below. Figure 18.5 shows the timing for the operation and release of the low-voltage detection circuit. 1. To operate the low-voltage detection circuit, set the LVDE bit in LVDCR to 1. 2. Wait for 50 s (tLVDON) until the reference voltage and the low-voltage-detection power supply have stabilized by a software timer, etc. Then, clear the LVDDF and LVDUF bits in LVDSR to 0 and set the LVDRE, LVDDE, and LVDUE bits in LVDCR to 1, as required. 3. To release the low-voltage detection circuit, start by clearing all of the LVDRE, LVDDE, and LVDUE bits to 0. Then clear the LVDE bit to 0. The LVDE bit must not be cleared to 0 at the same timing as the LVDRE, LVDDE, and LVDUE bits because incorrect operation may occur.
LVDE
LVDRE
LVDDE
LVDUE
tLVDON
Figure 18.5 Timing for Operation/Release of Low-Voltage Detection Circuit
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Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
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Section 19 Power Supply Circuit
Section 19 Power Supply Circuit
This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external VCC pin. As a result, the current consumed when an external power supply is used at 3.0 V or above can be held down to virtually the same low level as when used at approximately 3.0 V. If the external power supply is 3.0 V or below, the internal voltage will be practically the same as the external voltage. It is, of course, also possible to use the same level of external power supply voltage and internal power supply voltage without using the internal power supply step-down circuit.
19.1
When Using Internal Power Supply Step-Down Circuit
Connect the external power supply to the VCC pin, and connect a capacitance of approximately 0.1 F between VCL and VSS, as shown in figure 19.1. The internal step-down circuit is made effective simply by adding this external circuit. In the external circuit interface, the external power supply voltage connected to VCC and the GND potential connected to VSS are the reference levels. For example, for port input/output levels, the VCC level is the reference for the high level, and the VSS level is that for the low level. The A/D converter analog power supply is not affected by the internal step-down circuit.
VCC VCC = 3.0 to 5.5 V
Step-down circuit
VCL
Internal logic
Internal power supply
Stabilization capacitance (approx. 0.1 F)
VSS
Figure 19.1 Power Supply Connection when Internal Step-Down Circuit is Used
PSCKT00A_000020020200
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Section 19 Power Supply Circuit
19.2
When Not Using Internal Power Supply Step-Down Circuit
When the internal power supply step-down circuit is not used, connect the external power supply to the VCL pin and VCC pin, as shown in figure 19.2. The external power supply is then input directly to the internal power supply. The permissible range for the power supply voltage is 3.0 V to 3.6 V. Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more than 3.6 V) is input.
VCC VCC = 3.0 to 3.6 V
Step-down circuit
VCL
Internal logic
Internal power supply
VSS
Figure 19.2 Power Supply Connection when Internal Step-Down Circuit is Not Used
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Section 20 List of Registers
Section 20 List of Registers
The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register addresses (address order) * Registers are listed from the lower allocation addresses. * The symbol in the register-name column represents a reserved address or range of reserved addresses. Do not attempt to access reserved addresses. * When the address is 16-bit wide, the address of the upper byte is given in the list. * Registers are classified by functional modules. * The data bus width is indicated. * The number of access states is indicated. 2. * * * Register bits Bit configurations of the registers are described in the same order as the register addresses. Reserved bits are indicated by in the bit name column. When registers consist of 16 bits, bits are described from the MSB side.
3. Register states in each operating mode * Register states are described in the same order as the register addresses. * The register states described here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
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Section 20 List of Registers
20.1
Register Addresses (Address Order)
The data-bus width column indicates the number of bits. The access-state column shows the number of states of the selected basic clock that is required for access to the register. Note: Access to undefined or reserved addresses should not take place. Correct operation of the access itself or later operations is not guaranteed when such a register is accessed.
Abbreviation
--
Register Name
--
Bit No
--
Address
Module Name
Data Bus Width
--
Access State
--
H'F000 to -- H'F72F H'F730 H'F731 LVDC*1 LVDC*1
Low-voltage detection control register
LVDCR
8 8
--
8 8
--
2 2
--
Low-voltage detection status register LVDSR
-- --
H'F732 to -- H'F747 H'F748 H'F749 H'F74A H'F74B H'F74C H'F74D H'F74E H'F74F IIC2 IIC2 IIC2 IIC2 IIC2 IIC2 IIC2 IIC2
I2C bus control register 1 I C bus control register 2 I C bus mode register I2C bus interrupt enable register I C bus status register Slave address register I C bus transmit data register I C bus receive data register
--
2 2 2 2 2
ICCR1 ICCR2 ICMR ICIER ICSR SAR ICDRT ICDRR
--
8 8 8 8 8 8 8 8
--
8 8 8 8 8 8 8 8
--
2 2 2 2 2 2 2 2
--
H'F750 to -- H'FF7F H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 Timer W Timer W Timer W Timer W Timer W Timer W Timer W Timer W
Timer mode register W Timer control register W Timer interrupt enable register W Timer status register W Timer I/O control register 0 Timer I/O control register 1 Timer counter General register A
TMRW TCRW TIERW TSRW TIOR0 TIOR1 TCNT GRA
8 8 8 8 8 8 16 16
8 8 8 8 8 8 16* 16*
2 2
2 2 2 2 2 2 2 2
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Section 20 List of Registers
Register Name General register B General register C General register D Flash memory control register 1 Flash memory control register 2
Abbreviation GRB GRC GRD
Bit No 16 16 16
Address H'FF8A H'FF8C H'FF8E H'FF90 H'FF91 H'FF92 H'FF93
Module Name Timer W Timer W Timer W ROM ROM ROM ROM
Data Bus Width 16*2 16* 16* 8 8 8 8
--
2 2
Access State 2 2 2 2 2 2 2
--
FLMCR1 8 FLMCR2 8
Flash memory power control register FLPWCR 8 Erase block register 1
--
EBR1
--
8
--
H'FF94 to -- H'FF9A H'FF9B ROM
Flash memory enable register
--
FENR
--
8
--
8
--
2
--
H'FF9C to -- H'FF9F H'FFA0 H'FFA1 H'FFA2 H'FFA3 H'FFA4 H'FFA5 H'FFA6 H'FFA7 H'FFA8 H'FFA9 H'FFAA H'FFAB H'FFAC H'FFAD H'FFAE, H'FFAF H'FFB0 Timer V Timer V Timer V Timer V Timer V Timer V Timer A Timer A SCI3 SCI3 SCI3 SCI3 SCI3 SCI3
--
Timer control register V0 Timer control/status register V Timer constant register A Timer constant register B Timer counter V Timer control register V1 Timer mode register A Timer counter A Serial mode register Bit rate register Serial control register 3 Transmit data register Serial status register Receive data register
--
TCRV0 TCSRV TCORA TCORB TCNTV TCRV1 TMA TCA SMR BRR SCR3 TDR SSR RDR
--
8 8 8 8 8 8 8 8 8 8 8 8 8 8
--
8 8 8 8 8 8 8 8 8 8 8 8 8 8
--
3 3 3 3 3 3 2 2 3 3 3 3 3 3
--
A/D data register A
ADDRA
16
A/D converter
8
3
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Section 20 List of Registers
Register Name A/D data register B A/D data register C A/D data register D A/D control/status register A/D control register
--
Abbreviation ADDRB ADDRC ADDRD ADCSR ADCR
--
Bit No 16 16 16 8 8
--
Address H'FFB2 H'FFB4 H'FFB6 H'FFB8 H'FFB9
Module Name A/D converter A/D converter A/D converter A/D converter A/D converter
Data Bus Width 8 8 8 8 8
--
Access State 3 3 3 3 3
--
H'FFBA to -- H'FFBF H'FFC0 H'FFC1 H'FFC2 H'FFC3 WDT*3 WDT*3 WDT*
--
3
Timer control/status register WD Timer counter WD Timer mode register WD
-- --
TCSRW D TCWD TMWD
-- --
8 8 8
-- --
8 8 8
-- --
2 2 2
-- --
H'FFC4 to -- H'FFC7 H'FFC8 H'FFC9 H'FFCA H'FFCB H'FFCC H'FFCD H'FFCE, H'FFCF Address break Address break Address break Address break Address break Address break
--
Address break control register Address break status register Break address register H Break address register L Break data register H Break data register L
--
ABRKCR 8 ABRKSR 8 BARH BARL BDRH BDRL
--
8 8 8 8 8 8
--
2 2 2 2 2 2
--
8 8 8 8
--
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Section 20 List of Registers
Register Name Port pull-up control register 1 Port pull-up control register 5
--
Abbreviation PUCR1 PUCR5
--
Bit No 8 8
--
Address H'FFD0 H'FFD1 H'FFD2, H'FFD3 H'FFD4 H'FFD5 H'FFD6, H'FFD7 H'FFD8 H'FFD9 H'FFDA H'FFDB H'FFDC H'FFDD H'FFDE, H'FFDF H'FFE0 H'FFE1 H'FFE2, H'FFE3 H'FFE4 H'FFE5 H'FFE6, H'FFE7 H'FFE8 H'FFE9 H'FFEA H'FFEB
Module Name I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port
Data Bus Width 8 8
--
Access State 2 2
--
Port data register 1 Port data register 2
--
PDR1 PDR2
--
8 8 8 8
--
8 8
--
2 2
--
Port data register 5
--
PDR5
--
8
--
2
--
Port data register 7 Port data register 8
--
PDR7 PDR8
--
8 8
--
8 8
--
2 2
--
Port data register B
--
PDRB
--
8
--
8
--
2
--
Port mode register 1 Port mode register 5
--
PMR1 PMR5
--
8 8
--
8 8
--
2 2
--
Port control register 1 Port control register 2
--
PCR1 PCR2
--
8 8
--
8 8
--
2 2
--
Port control register 5
--
PCR5
--
8
--
8
--
2
--
Port control register 7 Port control register 8
--
PCR7 PCR8
--
8 8
--
8 8
--
2 2
--
H'FFEC to I/O port H'FFEF
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Section 20 List of Registers
Register Name System control register 1 System control register 2 Interrupt edge select register 1 Interrupt edge select register 2 Interrupt enable register 1
--
Abbreviation
Bit No
Address H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFE7 H'FFF8 H'FFF9
Module Name Power-down Power-down Interrupts Interrupts Interrupts I/O port Interrupts I/O port Interrupts Power-down
Data Bus Access Width State 8 8 8 8 8
--
SYSCR1 8 SYSCR2 8 IEGR1 IEGR2 IENR1
--
2 2 2 2 2
--
8 8 8
--
Interrupt flag register 1
--
IRR1
--
8
--
8
--
2
--
Wake-up interrupt flag register Module standby control register 1
--
IWPR
8
8 8
--
2 2
--
MSTCR1 8
-- --
H'FFFA to -- H'FFFF
* EEPROM
Abbreviation -- EKR Bit No 8 8 Module Name EEPROM EEPROM Data Bus Access Width State -- -- -- --
Register Name EEPROM slave address register EEPROM key register
Address H'FF09 H'FF10
Notes: 1. LVDC: Low-voltage detection circuits (optional) 2. Only word access can be used. 3. WDT: Watchdog timer
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Section 20 List of Registers
20.2
Register Bits
The addresses and bit names of the registers in the on-chip peripheral modules are listed below. The 16-bit register is indicated in two rows, 8 bits for each row.
Register Name -- LVDCR LVDSR -- ICCR1 ICCR2 ICMR ICIER ICSR SAR ICDRT ICDRR -- TMRW TCRW TIERW TSRW TIOR0 TIOR1 TCNT Bit 7 -- LVDE -- -- ICE BBSY MLS TIE TDRE SVA6 ICDRT7 ICDRR7 -- CTS CCLR OVIE OVF -- -- Bit 6 -- -- -- -- RCVD SCP WAIT TEIE TEND SVA5 ICDRT6 ICDRR6 -- -- CKS2 -- -- IOB2 IOD2 Bit 5 -- -- -- -- MST SDAO -- RIE RDRF SVA4 ICDRT5 ICDRR5 -- BUFEB CKS1 -- -- IOB1 IOD1 Bit 4 -- -- -- -- TRS SDAOP -- NAKIE NACKF SVA3 ICDRT4 ICDRR4 -- BUFEA CKS0 -- -- IOB0 IOD0 Bit 3 -- Bit 2 -- Bit 1 -- LVDDE LVDDF -- CKS1 IICRST BC1 ACKBR AAS SVA0 ICDRT1 ICDRR1 -- PWMC TOB IMIEB IMFB IOA1 IOC1 Bit 0 -- LVDUE LVDUF -- CKS0 -- BC0 ACKBT ADZ FS ICDRT0 ICDRR0 -- PWMB TOA IMIEA IMFA IOA0 IOC0 TCNT8 TCNT0 GRA8 GRA0 GRB8 GRB0 GRC8 GRC0 GRD8 GRD0 -- Timer W Module Name -- LVDC (optional)* -- IIC2
1
LVDSEL LVDRE -- -- CKS3 SCKO BCWP STIE STOP SVA2 ICDRT3 ICDRR3 -- -- TOD IMIED IMFD -- -- -- -- CKS2 -- BC2 ACKE AL/OVE SVA1 ICDRT2 ICDRR2 -- PWMD TOC IMIEC IMFC IOA2 IOC2
TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT7 TCNT6 GRA14 GRA6 GRB14 GRB6 GRC14 GRC6 GRD14 GRD6 TCNT5 GRA13 GRA5 GRB13 GRB5 GRC13 GRC5 GRD13 GRD5 TCNT4 GRA12 GRA4 GRB12 GRB4 GRC12 GRC4 GRD12 GRD4 TCNT3 GRA11 GRA3 GRB11 GRB3 GRC11 GRC3 GRD11 GRD3 TCNT2 GRA10 GRA2 GRB10 GRB2 GRC10 GRC2 GRD10 GRD2 TCNT1 GRA9 GRA1 GRB9 GRB1 GRC9 GRC1 GRD9 GRD1
GRA
GRA15 GRA7
GRB
GRB15 GRB7
GRC
GRC15 GRC7
GRD
GRD15 GRD7
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Section 20 List of Registers Register Name FLMCR1 FLMCR2 FLPWCR EBR1 FENR TCRV0 TCSRV TCORA TCORB TCNTV TCRV1 TMA TCA SMR BRR SCR3 TDR SSR RDR ADDRA Module Name ROM
Bit 7 -- FLER
Bit 6 SWE --
Bit 5 ESU -- -- -- -- OVIE OVF
Bit 4 PSU -- -- EB4 -- CCLR1 --
Bit 3 EV -- -- EB3 -- CCLR0 OS3
Bit 2 PV -- -- EB2 -- CKS2 OS2
Bit 1 E -- -- EB1 -- CKS1 OS1
Bit 0 P -- -- EB0 -- CKS0 OS0
PDWND -- -- FLSHE CMIEB CMFB -- -- CMIEA CMFA
Timer V
TCORA7 TCORA6 TCORA5 TCORA4 TCORA3 TCORA2 TCORA1 TCORA0 TCORB7 TCORB6 TCORB5 TCORB4 TCORB3 TCORB2 TCORB1 TCORB0 TCNTV7 TCNTV6 TCNTV5 TCNTV4 TCNTV3 TCNTV2 TCNTV1 TCNTV0 -- TMA7 TCA7 COM BRR7 TIE TDR7 TDRE RDR7 AD9 AD1 -- TMA6 TCA6 CHR BRR6 RIE TDR6 RDRF RDR6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE -- -- TCWE TCWD6 -- TMA5 TCA5 PE BRR5 TE TDR5 OER RDR5 AD7 -- AD7 -- AD7 -- AD7 -- ADST -- -- B4WI TCWD5 TVEG1 -- TCA4 PM BRR4 RE TDR4 FER RDR4 AD6 -- AD6 -- AD6 -- AD6 -- SCAN -- -- TCSRW E TCWD4 TVEG0 TMA3 TCA3 STOP BRR3 MPIE TDR3 PER RDR3 AD5 -- AD5 -- AD5 -- AD5 -- CKS -- -- B2WI TCWD3 TRGE TMA2 TCA2 MP BRR2 TEIE TDR2 TEND RDR2 AD4 -- AD4 -- AD4 -- AD4 -- CH2 -- -- WDON TCWD2 -- TMA1 TCA1 CKS1 BRR1 CKE1 TDR1 MPBR RDR1 AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- -- B0WI TCWD1 ICKS0 TMA0 TCA0 CKS0 BRR0 CKE0 TDR0 MPBT RDR0 AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- -- WRST TCWD0 -- WDT*2 A/D converter SCI3 Timer A
ADDRB
AD9 AD1
ADDRC
AD9 AD1
ADDRD
AD9 AD1
ADCSR ADCR --
ADF TRGE --
TCSRWD B6WI TCWD TCWD7
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Section 20 List of Registers Register Name TMWD -- ABRKCR ABRKSR BARH BARL BDRH BDRL -- PUCR1 PUCR5 PDR1 PDR2 PDR5 PDR7 PDR8 PDRB PMR1 PMR5 PCR1 PCR2 PCR5 PCR7 PCR8 SYSCR1 SYSCR2 IEGR1 IEGR2 IENR1 IRR1 IWPR MSTCR1 -- Module Name WDT*2 -- Address break
Bit 7 -- -- RTINTE ABIF BARH7 BARL7 BDRH7 BDRL7 --
Bit 6 -- -- CSEL1 ABIE BARH6 BARL6 BDRH6 BDRL6 --
Bit 5 -- -- CSEL0 -- BARH5 BARL5 BDRH5 BDRL5 --
Bit 4 -- -- ACMP2 -- BARH4 BARL4 BDRH4 BDRL4 --
Bit 3 CKS3 -- ACMP1 -- BARH3 BARL3 BDRH3 BDRL3 --
Bit 2 CKS2 -- ACMP0 -- BARH2 BARL2 BDRH2 BDRL2 --
Bit 1 CKS1 -- DCMP1 -- BARH1 BARL1 BDRH1 BDRL1 --
Bit 0 CKS0 -- DCMP0 -- BARH0 BARL0 BDRH0 BDRL0 --
--
PUCR17 PUCR16 PUCR15 PUCR14 -- -- P17 -- P57* -- P87 PB7 IRQ3 -- PCR17 -- PCR57* -- PCR87 SSBY SMSEL NMIEG -- IENDT IRRDT -- -- --
3 3
PUCR12 PUCR11 PUCR10 I/O port
-- P16 -- P56* P76 P86 PB6 IRQ2 -- PCR16 -- PCR56* PCR76 PCR86 STS2 LSON -- -- IENTA IRRTA -- MSTIIC --
3 3
PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 P15 -- P55 P75 P85 PB5 IRQ1 WKP5 PCR15 -- PCR55 PCR75 PCR85 STS1 DTON -- WPEG5 IENWP -- IWPF5 MSTS3 -- P14 -- P54 P74 P84 PB4 IRQ0 WKP4 PCR14 -- PCR54 PCR74 PCR84 STS0 MA2 -- WPEG4 -- -- IWPF4 MSTAD -- -- -- P53 -- P83 PB3 -- WKP3 -- -- PCR53 -- PCR83 NESEL MA1 IEG3 WPEG3 IEN3 IRRI3 IWPF3 P12 P22 P52 -- P82 PB2 -- WKP2 PCR12 PCR22 PCR52 -- PCR82 -- MA0 IEG2 WPEG2 IEN2 IRRI2 IWPF2 P11 P21 P51 -- P81 PB1 TXD WKP1 PCR11 PCR21 PCR51 -- PCR81 -- SA1 IEG1 WPEG1 IEN1 IRRI1 IWPF1 MSTTV -- P10 P20 P50 -- P80 PB0 TMOW WKP0 PCR10 PCR20 PCR50 -- PCR80 -- SA0 IEG0 WPEG0 IEN0 IRRI0 IWPF0 MSTTA -- Power-down -- Interrupts Power-down
MSTWD MSTTW -- --
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Section 20 List of Registers
* EEPROM
Register Name EKR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name EEPROM
Notes: 1. LVDC: Low-voltage detection circuits (optional) 2. WDT: Watchdog timer TM 3. These bits are reserved in the EEPROM stacked F-ZTAT and mask-ROM versions.
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Section 20 List of Registers
20.3
Register Name LVDCR LVDSR ICCR1 ICCR2 ICMR ICIER ICSR SAR ICDRT ICDRR TMRW TCRW TIERW TSRW TIOR0 TIOR1 TCNT GRA GRB GRC GRD FLMCR1 FLMCR2 FLPWCR EBR1 FENR TCRV0 TCSRV TCORA TCORB
Registers States in Each Operating Mode
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Active Sleep Subactive Subsleep Standby Module LVDC (optional)* IIC2
1
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Initialized
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Initialized
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Initialized
Timer W
ROM
-- --
Initialized
-- --
Initialized
-- --
Initialized
--
Initialized Initialized Initialized Initialized
--
Initialized Initialized Initialized Initialized
--
Initialized Initialized Initialized Initialized Timer V
Rev.5.00 Nov. 02, 2005 Page 311 of 418 REJ09B0028-0500
Section 20 List of Registers Register Name TCNTV TCRV1 TMA TCA SMR BRR SCR3 TDR SSR RDR ADDRA ADDRB ADDRC ADDRD ADCSR ADCR
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Active
Sleep
Subactive Initialized Initialized
Subsleep Initialized Initialized
Standby Initialized Initialized
Module Timer V
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- --
Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
-- --
Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
-- --
Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Timer A
SCI3
A/D converter
TCSRWD Initialized TCWD TMWD ABRKCR ABRKSR BARH BARL BDRH BDRL PUCR1 PUCR5 PDR1 PDR2 PDR5 PDR7 PDR8 PDRB Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
WDT*
2
Address Break
I/O port
Rev.5.00 Nov. 02, 2005 Page 312 of 418 REJ09B0028-0500
Section 20 List of Registers Register Name PMR1 PMR5 PCR1 PCR2 PCR5 PCR7 PCR8 SYSCR1 SYSCR2 IEGR1 IEGR2 IENR1 IRR1 IWPR MSTCR1
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Active
Sleep
Subactive
Subsleep
Standby
Module I/O port
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Power-down Power-down Interrupts Interrupts Interrupts Interrupts Interrupts Power-down
* EEPROM
Register Name EKR Reset Active Sleep Subactive Subsleep Standby Module EEPROM
--
--
--
--
--
--
Notes: is not initialized 1. LVDC: Low-voltage detection circuits (optional) 2. WDT: Watchdog timer
Rev.5.00 Nov. 02, 2005 Page 313 of 418 REJ09B0028-0500
Section 20 List of Registers
Rev.5.00 Nov. 02, 2005 Page 314 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
Section 21 Electrical Characteristics
21.1 Absolute Maximum Ratings
Table 21.1 Absolute Maximum Ratings
Item Power supply voltage Analog power supply voltage Input voltage Ports other than ports B and X1 Port B X1 Operating temperature Storage temperature Note: * Topr Tstg Symbol VCC AVCC VIN Value -0.3 to +7.0 -0.3 to +7.0 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to 4.3 -20 to +75 -55 to +125 Unit V V V V V C C Note *
Permanent damage may result if maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability.
21.2
Electrical Characteristics (F-ZTATTM Version, EEPROM Stacked F-ZTATTM Version)
Power Supply Voltage and Operating Ranges
21.2.1
Power Supply Voltage and Oscillation Frequency Range
OSC (MHz)
W (kHz)
20.0
32.768
10.0
2.0
3.0
4.0
5.5
VCC (V)
3.0
4.0
5.5
VCC (V)
* AVCC = 3.3 to 5.5 V * Active mode * Sleep mode
* AVCC = 3.3 to 5.5 V * All operating modes
Rev.5.00 Nov. 02, 2005 Page 315 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
Power Supply Voltage and Operating Frequency Range
(MHz) 20.0 16.384 10.0 8.192 1.0 3.0 4.0 5.5 VCC (V) 4.096 3.0 4.0 5.5 VCC (V) SUB (kHz)
* AVCC = 3.3 to 5.5 V * Active mode * Sleep mode (When MA2 in SYSCR2 = 0 ) (kHz) 2500 1250
* AVCC = 3.3 to 5.5 V * Subactive mode * Subsleep mode
78.125 3.0 4.0 5.5 VCC (V) * AVCC = 3.3 to 5.5 V * Active mode * Sleep mode (When MA2 in SYSCR2 = 1 )
Analog Power Supply Voltage and A/D Converter Accuracy Guarantee Range
(MHz)
20.0 10.0
2.0 3.3 4.0 5.5 AVCC (V)
* VCC = 3.0 to 5.5 V * Active mode * Sleep mode
Rev.5.00 Nov. 02, 2005 Page 316 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage Detection Circuit is Used
osc (MHz)
20.0 16.0
2.0 Vcc(V) 3.0 4.5 5.5
Operation guarantee range Operation guarantee range except A/D conversion accuracy
Rev.5.00 Nov. 02, 2005 Page 317 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
21.2.2
DC Characteristics
Table 21.2 DC Characteristics (1) VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Values Item Symbol Applicable Pins Test Condition Min VCC x 0.8 Typ -- Max VCC + 0.3 Unit V Notes VCC = 4.0 to 5.5 V RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG,TMRIV, TMCIV, FTCI, FTIOA to FTIOD, SCK3, TRGV RXD, SCL, SDA, VCC = 4.0 to 5.5 V P10 to P12, P14 to P17, P20 to P22, P50 to P57, P74 to P76, P80 to P87 PB0 to PB7 VCC = 4.0 to 5.5 V
Input high VIH voltage
VCC x 0.9
--
VCC + 0.3
VCC x 0.7
--
VCC + 0.3
V
VCC x 0.8
--
VCC + 0.3
VCC x 0.7 VCC x 0.8 VCC - 0.5 VCC - 0.3 -0.3
-- -- -- -- --
AVCC + 0.3 V AVCC + 0.3 VCC + 0.3 VCC + 0.3 VCC x 0.2 V V
OSC1
VCC = 4.0 to 5.5 V
Input low voltage
VIL
VCC = 4.0 to 5.5 V RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG,TMRIV, TMCIV, FTCI, FTIOA to FTIOD, SCK3, TRGV RXD, SCL, SDA, VCC = 4.0 to 5.5 V P10 to P12, P14 to P17, P20 to P22, P50 to P57, P74 to P76, P80 to P87 PB0 to PB7 OSC1 VCC = 4.0 to 5.5 V
-0.3
--
VCC x 0.1
-0.3
--
VCC x 0.3
V
-0.3
--
VCC x 0.2
-0.3 -0.3
-- --
0.5 0.3
V
Rev.5.00 Nov. 02, 2005 Page 318 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics Values Item Output high voltage Symbol VOH Applicable Pins P10 to P12, P14 to P17, P20 to P22, P50 to P55, P74 to P76, P80 to P87 P56, P57 Test Condition Min Typ -- Max -- Unit V Notes
VCC = 4.0 to 5.5 V VCC - 1.0 -IOH = 1.5 mA -IOH = 0.1 mA VCC - 0.5
--
--
VCC = 4.0 to 5.5 V VCC - 2.5 -IOH = 0.1 mA VCC = 3.0 to 4.0 V VCC - 2.0 -IOH = 0.1 mA
--
--
V
--
--
Output low voltage
VOL
P10 to P12, P14 to P17, P20 to P22, P50 to P57, P74 to P76 P80 to P87
VCC = 4.0 to 5.5 VIOL = 1.6 mA IOL = 0.4 mA
--
--
0.6
V
--
-- --
0.4 1.5 V
VCC = 4.0 to 5.5 V -- IOL = 20.0 mA VCC = 4.0 to 5.5 V -- IOL = 10.0 mA VCC = 4.0 to 5.5 V -- IOL = 1.6 mA IOL = 0.4 mA --
--
1.0
--
0.4
-- --
0.4 0.6 V
SCL, SDA
VCC = 4.0 to 5.5 V -- IOL = 6.0 mA IOL = 3.0 mA -- --
-- --
0.4 1.0 A
Input/ output leakage current
| IIL |
VIN = 0.5 V to OSC1, NMI, WKP0 to WKP5, (VCC - 0.5 V) IRQ0 to IRQ3, ADTRG, TRGV, TMRIV, TMCIV, FTCI, FTIOA to FTIOD, RXD, SCK3, SCL, SDA P10 to P12, P14 to P17, P20 to P22, P50 to P57, P74 to P76, P80 to P87 PB0 to PB7 VIN = 0.5 V to (VCC - 0.5 V)
--
--
1.0
A
VIN = 0.5 V to (AVCC - 0.5 V)
--
--
1.0
A
Rev.5.00 Nov. 02, 2005 Page 319 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics Values Item Pull-up MOS current Symbol -Ip Applicable Pins P10 to P12, P14 to P17, P50 to P55 Test Condition VCC = 5.0 V, VIN = 0.0 V VCC = 3.0 V, VIN = 0.0 V f = 1 MHz, VIN = 0.0 V, Ta = 25C Active mode 1 VCC = 5.0 V, fOSC = 20 MHz Active mode 1 VCC = 3.0 V, fOSC = 10 MHz VCC Active mode 2 VCC = 5.0 V, fOSC = 20 MHz Active mode 2 VCC = 3.0 V, fOSC = 10 MHz ISLEEP1 Sleep mode current consumption VCC Sleep mode 1 VCC = 5.0 V, fOSC = 20 MHz Sleep mode 1 VCC = 3.0 V, fOSC = 10 MHz VCC Sleep mode 2 VCC = 5.0 V, fOSC = 20 MHz Sleep mode 2 VCC = 3.0 V, fOSC = 10 MHz Subactive ISUB mode current consumption VCC VCC = 3.0 V 32-kHz crystal resonator (SUB = W/2) VCC = 3.0 V 32-kHz crystal resonator (SUB = W/8) Min 50.0 -- -- Typ -- 60.0 -- Max 300.0 -- 15.0 pF Unit Notes A Reference value
Input capacitance
Cin
All input pins except power supply pins SDA, SCL
-- --
-- 20.0
25.0 30.0
pF mA
HD64N3694G *
IOPE1 Active mode current consumption
VCC
--
8.0
--
* Reference value mA *
IOPE2
--
2.0
3.0
--
1.2
--
* Reference value mA *
--
16.0
22.5
--
8.0
--
* Reference value mA *
ISLEEP2
--
1.8
2.7
--
1.2
--
* Reference value A *
--
40.0
70.0
--
30.0
--
* Reference value
Rev.5.00 Nov. 02, 2005 Page 320 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics Values Item Symbol Applicable Pins VCC Test Condition VCC = 3.0 V 32-kHz crystal resonator (SUB = W/2) 32-kHz crystal resonator not used Min -- Typ 30.0 Max 50.0 Unit A Notes *
Subsleep ISUBSP mode current consumption ISTBY Standby mode current consumption RAM data VRAM retaining voltage
VCC
--
--
5.0
A
*
VCC
2.0
--
--
V
Note:
*
Pin states during current consumption measurement are given below (excluding current in the pull-up MOS transistors and output buffers).
RES Pin VCC Internal State Operates Other Pins VCC Oscillator Pins Main clock: ceramic or crystal resonator Subclock: Pin X1 = VSS VCC
Mode Active mode 1
Active mode 2 Sleep mode 1 Sleep mode 2 Subactive mode VCC VCC
Operates (OSC/64) Only timers operate Only timers operate (OSC/64) Operates VCC
Main clock: ceramic or crystal resonator Subclock: crystal resonator Main clock: ceramic or crystal resonator Subclock: Pin X1 = VSS
Subsleep mode Standby mode
VCC VCC
Only timers operate CPU and timers both stop
VCC VCC
Rev.5.00 Nov. 02, 2005 Page 321 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
Table 21.2 DC Characteristics (2) VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise indicated.
Values Item EEPROM current consumption Symbol IEEW IEER IEESTBY Applicable Pins VCC VCC VCC Test Condition VCC = 5.0 V, tSCL = 2.5 s (when writing) VCC = 5.0 V, tSCL = 2.5 s (when reading) VCC = 5.0 V, tSCL = 2.5 s (at standby) Min -- -- -- Typ -- -- -- Max 2.0 0.3 3.0 Unit mA mA A Notes *
Note:
*
The current consumption of the EEPROM chip is shown. For the current consumption of H8/3694N, add the above current values to the current consumption of H8/3694F.
Rev.5.00 Nov. 02, 2005 Page 322 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
Table 21.2 DC Characteristics (3) VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Applicable Item Allowable output low current (per pin) Symbol IOL Pins Output pins except port 8, SCL, and SDA Port 8 Port 8 SCL and SDA Output pins except port 8, SCL, and SDA Allowable output low current (total) IOL Output pins except port 8, SCL, and SDA Port 8, SCL, and SDA Output pins except port 8, SCL, and SDA Port 8, SCL, and SDA Allowable output high -IOH current (per pin) Allowable output high -IOH current (total) All output pins All output pins Test Condition Min Values Typ -- Max 2.0 Unit mA
VCC = 4.0 to 5.5 V --
-- -- -- --
-- -- -- --
20.0 10.0 6.0 0.5
VCC = 4.0 to 5.5 V --
--
40.0
mA
-- --
-- --
80.0 20.0
-- VCC = 4.0 to 5.5 V -- -- VCC = 4.0 to 5.5 V -- --
-- -- -- -- --
40.0 2.0 0.2 30.0 8.0 mA mA
Rev.5.00 Nov. 02, 2005 Page 323 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
21.2.3
AC Characteristics
Table 21.3 AC Characteristics VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Applicable Pins Values Test Condition Min 2.0 2.0 tcyc X1, X2 X1, X2 1 -- -- -- 2 2 trc OSC1, OSC2 OSC1, OSC2 X1, X2 OSC1 OSC1 OSC1 OSC1 RES VCC = 4.0 to 5.5 V VCC = 4.0 to 5.5 V VCC = 4.0 to 5.5 V VCC = 4.0 to 5.5 V -- -- -- Typ -- Max 20.0 10.0 64 12.8 tOSC s kHz s tW tcyc tsubcyc ms *
2
Item System clock oscillation frequency System clock () cycle time
Symbol fOSC
Unit MHz
Reference Figure *
1
OSC1, OSC2 VCC = 4.0 to 5.5 V
*
2
Subclock oscillation fW frequency Watch clock (W) cycle time Subclock (SUB) cycle time Instruction cycle time Oscillation stabilization time (crystal resonator) tW tsubcyc
32.768 -- 30.5 -- -- -- -- 8 -- 10.0
Oscillation trc stabilization time (ceramic resonator) Oscillation stabilization time External clock high width External clock low width External clock rise time External clock fall time RES pin low width tREL tCPf tCPr tCPL trcx tCPH
--
--
5.0
ms
-- 20.0 40.0 20.0 40.0 -- -- -- -- At power-on and in trc modes other than those below In active mode and 200 sleep mode operation
-- -- -- -- -- -- -- -- -- --
2.0 -- -- -- -- 10.0 15.0 10.0 15.0 --
s ns ns ns ns ms Figure 21.2 Figure 21.1
--
--
ns
Rev.5.00 Nov. 02, 2005 Page 324 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics Values Test Condition Min 2 Typ -- Max -- Unit tcyc tsubcyc
Item Input pin high width
Symbol tIH
Applicable Pins NMI, IRQ0 to IRQ3, WKP0 to WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTCI, FTIOA to FTIOD NMI, IRQ0 to IRQ3, WKP0 to WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTCI, FTIOA to FTIOD
Reference Figure Figure 21.3
Input pin low width
tIL
2
--
--
tcyc tsubcyc
Notes: 1. When an external clock is input, the minimum system clock oscillation frequency is 1.0 MHz. 2. Determined by MA2, MA1, MA0, SA1, and SA0 of system control register 2 (SYSCR2).
Rev.5.00 Nov. 02, 2005 Page 325 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
Table 21.4 I2C Bus Interface Timing VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Test Condition Values Min 3tcyc + 300 5tcyc + 300 -- -- Typ -- -- -- -- Max -- -- -- 300 1tcyc Unit ns ns ns ns ns 12tcyc + 600 -- Reference Figure Figure 21.4
Item SCL input cycle time SCL input high width SCL input low width SCL and SDA input fall time SCL and SDA input spike pulse removal time SDA input bus-free time Start condition input hold time Retransmission start condition input setup time Setup time for stop condition input Data-input hold time Capacitive load of SCL and SDA SCL and SDA output fall time
Symbol tSCL tSCLH tSCLL tSf tSP
tBUF tSTAH tSTAS
5tcyc 3tcyc 3tcyc
-- -- --
-- -- --
ns ns ns
tSTOS
3tcyc 1tcyc+20 0 0 VCC = 4.0 to -- 5.5 V --
-- -- -- -- -- --
-- -- -- 400 250 300
ns ns ns pF ns
Data-input setup time tSDAS tSDAH cb tSf
Rev.5.00 Nov. 02, 2005 Page 326 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
Table 21.5 Serial Communication Interface (SCI) Timing VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Applicable Pins SCK3 Values Test Condition Min 4 6 Typ Max Unit -- -- -- -- tcyc Reference Figure Figure 21.5
Item Input clock cycle Asynchronous Clocked synchronous
Symbol tScyc
Input clock pulse width Transmit data delay time (clocked synchronous) Receive data setup time (clocked synchronous) Receive data hold time (clocked synchronous)
tSCKW tTXD
SCK3 TXD VCC = 4.0 V to 5.5 V
0.4 -- --
-- -- -- --
0.6 1 1 -- -- -- --
tScyc tcyc Figure 21.6
tRXS
RXD
VCC = 4.0 V to 5.5 V
50.0
ns
100.0 -- tRXH RXD VCC = 4.0 V to 5.5 V 50.0 --
ns
100.0 --
Rev.5.00 Nov. 02, 2005 Page 327 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
21.2.4
A/D Converter Characteristics
Table 21.6 A/D Converter Characteristics VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Applicable Pins AVCC AN0 to AN7 AVCC Test Condition Values Min 3.3 VSS - 0.3 AVCC = 5.0 V -- fOSC = 20 MHz AVCC -- 50 -- A * Reference value *
3 2
Item
Symbol
Typ Max VCC -- -- 5.5
Unit V
Reference Figure *
1
Analog power supply AVCC voltage Analog input voltage AVIN Analog power supply AIOPE current
AVCC + 0.3 V 2.0 mA
AISTOP1
AISTOP2 Analog input capacitance Allowable signal source impedance Resolution (data length) Conversion time (single mode) Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Conversion time (single mode) Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy CAIN RAIN
AVCC AN0 to AN7 AN0 to AN7
-- -- -- 10 AVCC = 3.3 to 134 5.5 V -- -- -- -- -- AVCC = 4.0 to 70 5.5 V -- -- -- -- --
-- -- -- 10 -- -- -- -- -- -- -- -- -- -- -- --
5.0 30.0 5.0 10 -- 7.5 7.5 7.5 0.5 8.0 -- 7.5 7.5 7.5 0.5 8.0
A pF k bit tcyc LSB LSB LSB LSB LSB tcyc LSB LSB LSB LSB LSB
Rev.5.00 Nov. 02, 2005 Page 328 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics Values Min Typ Max -- -- -- -- -- -- -- 3.5 3.5 3.5 0.5 4.0 Unit tcyc LSB LSB LSB LSB LSB
Item Conversion time (single mode) Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy
Symbol
Applicable Pins
Test Condition
Reference Figure
AVCC = 4.0 to 134 5.5 V -- -- -- -- --
Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at reset and in standby, subactive, and subsleep modes while the A/D converter is idle.
21.2.5
Watchdog Timer Characteristics
Table 21.7 Watchdog Timer Characteristics VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Applicable Pins Test Condition Values Min 0.2 Typ 0.4 Max -- Unit s Reference Figure *
Item On-chip oscillator overflow time Note: *
Symbol tOVF
Shows the time to count from 0 to 255, at which point an internal reset is generated, when the internal oscillator is selected.
Rev.5.00 Nov. 02, 2005 Page 329 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
21.2.6
Flash Memory Characteristics
Table 21.8 Flash Memory Characteristics VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Test Condition Values Min -- -- 1000 1 50 1n6 7 n 1000 Additionalprogramming 28 198 8 5 5 4 2 2 100 -- Typ 7 100 10000 -- -- 30 200 10 -- -- -- -- -- -- -- Max 200 1200 -- -- -- 32 202 12 -- -- -- -- -- -- 1000 Unit ms ms Times s s s s s s s s s s s Times
Item Programming time (per 128 bytes)* * * Erase time (per block) * * * Reprogramming count Programming Wait time after SWE 1 bit setting* Wait time after PSU 1 bit setting* Wait time after P bit setting **
14 136 124
Symbol tP tE NWEC x y z1 z2 z3 Wait time after P bit clear* Wait time after PSU 1 bit clear* Wait time after PV 1 bit setting* Wait time after 1 dummy write* Wait time after PV bit clear* Wait time after SWE 1 bit clear* Maximum programming 145 count * * *
1 1
N
Rev.5.00 Nov. 02, 2005 Page 330 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics Values Min 1 100 10 10 10 20 2 4 100 -- Typ -- -- -- -- -- -- -- -- -- -- Max -- -- 100 -- -- -- -- -- -- 120 Unit s s ms s s s s s s Times
Item Erasing Wait time after SWE 1 bit setting* Wait time after ESU 1 bit setting* Wait time after E bit 16 setting* * Wait time after E bit clear* Wait time after ESU 1 bit clear* Wait time after EV 1 bit setting* Wait time after 1 dummy write* Wait time after EV bit clear* Wait time after SWE 1 bit clear* Maximum erase count * * *
167 1 1
Symbol x y z N
Test Condition
Notes: 1. Make the time settings in accordance with the program/erase algorithms. 2. The programming time for 128 bytes. (Indicates the total time for which the P bit in flash memory control register 1 (FLMCR1) is set. The program-verify time is not included.) 3. The time required to erase one block. (Indicates the time for which the E bit in flash memory control register 1 (FLMCR1) is set. The erase-verify time is not included.) 4. Programming time maximum value (tP (max.)) = wait time after P bit setting (z) x maximum programming count (N) 5. Set the maximum programming count (N) according to the actual set values of z1, z2, and z3, so that it does not exceed the programming time maximum value (tP (max.)). The wait time after P bit setting (z1, z2) should be changed as follows according to the value of the programming count (n). Programming count (n) 1n6 z1 = 30 s 7 n 1000 z2 = 200 s 6. Erase time maximum value (tE (max.)) = wait time after E bit setting (z) x maximum erase count (N) 7. Set the maximum erase count (N) according to the actual set value of (z), so that it does not exceed the erase time maximum value (tE (max.)).
Rev.5.00 Nov. 02, 2005 Page 331 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
21.2.7
EEPROM Characteristics
Table 21.9 EEPROM Characteristics VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Test Condition Min 2500 600 1200 1200 600 600 600 160 0 50 0 100 Values Typ Max 50 300 300 400 900 10 13 Reference Unit Figure ns s ns ns ns ns ns ns ns ns ns ns ns pF ns ms ms Figure 21.7
Item SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input spike pulse removal time SDA input bus-free time Start condition input hold time Retransmit start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA input fall time SDA input rise time Data output hold time SCL, SDA capacitive load Access time Cycle time at writing* Reset release time Note: *
Symbol tSCL tSCLH tSCLL tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH tSf tSr tDH Cb tAA tWC tRES
Cycle time at writing is a time from the stop condition to write completion (internal control).
Rev.5.00 Nov. 02, 2005 Page 332 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
21.2.8
Power-Supply-Voltage Detection Circuit Characteristics (Optional)
Table 21.10 Power-Supply-Voltage Detection Circuit Characteristics VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Test Condition LVDSEL = 0 LVDSEL = 0 LVDSEL = 0 LVDSEL = 1 Values Min 3.3 -- -- 3.0 1.0 50 LVDE = 1, Vcc = 5.0 V, When a 32kHz crystal resonator is not used Typ 3.7 4.0 2.3 3.6 -- -- -- Max -- 4.5 2.7 4.2 -- -- 350 Unit V V V V V s A
Item
Symbol Vint (D) Vint (U) Vreset1 Vreset2 VLVDRmin tLVDON ISTBY
Power-supply falling detection voltage Power-supply rising detection voltage Reset detection voltage 1*1 Reset detection voltage 2*
2
Lower-limit voltage of LVDR 3 operation* LVD stabilization time Current consumption in standby mode
Notes: 1. This voltage should be used when the falling and rising voltage detection function is used. 2. Select the low-voltage reset 2 when only the low-voltage detection reset is used. 3. When the power-supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises, a reset may not occur. Therefore sufficient evaluation is required.
Rev.5.00 Nov. 02, 2005 Page 333 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
21.2.9
Power-On Reset Circuit Characteristics (Optional)
Table 21.11 Power-On Reset Circuit Characteristics VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Values Item Symbol RRES Vpor Test Condition Min 100 -- Typ 150 -- Max -- 100 Unit k mV
Pull-up resistance of RES pin Power-on reset start voltage* Note: *
The power-supply voltage (Vcc) must fall below Vpor = 100 mV and then rise after charge of the RES pin is removed completely. In order to remove charge of the RES pin, it is recommended that the diode be placed in the Vcc side. If the power-supply voltage (Vcc) rises from the point over 100 mV, a power-on reset may not occur.
21.3
Electrical Characteristics (Mask-ROM Version, EEPROM Stacked Mask-ROM Version)
Power Supply Voltage and Operating Ranges
21.3.1
Power Supply Voltage and Oscillation Frequency Range
OSC (MHz)
W (kHz)
20.0
32.768
10.0
2.0
2.7
4.0
5.5
VCC (V)
2.7
4.0
5.5
VCC (V)
* AVCC = 3.0 to 5.5 V * Active mode * Sleep mode
* AVCC = 3.0 to 5.5 V * All operating modes
Rev.5.00 Nov. 02, 2005 Page 334 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
Power Supply Voltage and Operating Frequency Range
(MHz)
SUB (kHz)
20.0
16.384
10.0
8.192
1.0 2.7 4.0 5.5 VCC (V)
4.096
2.7
4.0
5.5
VCC (V)
(kHz)
* AVCC = 3.0 to 5.5 V * Active mode * Sleep mode (When MA2 in SYSCR2 = 0)
* AVCC = 3.0 to 5.5 V * Subactive mode * Subsleep mode
2500 1250
78.125 2.7 4.0 5.5 VCC (V) * AVCC = 3.0 to 5.5 V * Active mode * Sleep mode (When MA2 in SYSCR2 = 1)
Rev.5.00 Nov. 02, 2005 Page 335 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
Analog Power Supply Voltage and A/D Converter Accuracy Guarantee Range
(MHz)
20.0 10.0
2.0 3.0 4.0 5.5 AVCC (V)
* VCC = 2.7 to 5.5 V * Active mode * Sleep mode
Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage Detection Circuit is Used
osc (MHz)
20.0 16.0
2.0 Vcc(V) 3.0 4.5 5.5
Operation guarantee range Operation guarantee range except A/D conversion accuracy
Rev.5.00 Nov. 02, 2005 Page 336 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
21.3.2
DC Characteristics
Table 21.12 DC Characteristics (1) VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Values Item Symbol Applicable Pins Test Condition Min VCC x 0.8 Typ -- Max VCC + 0.3 Unit V Notes RES, NMI, VCC = 4.0 to 5.5 V WKP0 to WKP5, IRQ0 to IRQ3, ADTRG,TMRIV, TMCIV, FTCI, FTIOA to FTIOD, SCK3, TRGV RXD, SCL, SDA, P10 to P12, P14 to P17, P20 to P22, P50 to P57, P74 to P76, P80 to P87 PB0 to PB7 VCC = 4.0 to 5.5 V
Input high VIH voltage
VCC x 0.9
--
VCC + 0.3
VCC x 0.7
--
VCC + 0.3
V
VCC x 0.8
--
VCC + 0.3
VCC = 4.0 to 5.5 V
VCC x 0.7 VCC x 0.8 VCC - 0.5 VCC - 0.3 -0.3
-- -- -- -- --
AVCC + 0.3 V AVCC + 0.3 VCC + 0.3 VCC + 0.3 VCC x 0.2 V V
OSC1
VCC = 4.0 to 5.5 V
Input low VIL voltage
VCC = 4.0 to 5.5 V RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG,TMRIV, TMCIV, FTCI, FTIOA to FTIOD, SCK3, TRGV RXD, SCL, SDA, P10 to P12, P14 to P17, P20 to P22, P50 to P57, P74 to P76, P80 to P87, PB0 to PB7 OSC1 VCC = 4.0 to 5.5 V
-0.3
--
VCC x 0.1
-0.3
--
VCC x 0.3
V
-0.3
--
VCC x 0.2
VCC = 4.0 to 5.5 V
-0.3 -0.3
-- --
0.5 0.3
V
Rev.5.00 Nov. 02, 2005 Page 337 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics Values Item Output high voltage Symbol VOH Applicable Pins P10 to P12, P14 to P17, P20 to P22, P50 to P55, P74 to P76, P80 to P87 P56, P57 Test Condition Min Typ -- Max -- Unit V Notes
VCC = 4.0 to 5.5 V VCC - 1.0 -IOH = 1.5 mA -IOH = 0.1 mA VCC - 0.5
--
--
VCC = 4.0 to 5.5 V VCC - 2.5 -IOH = 0.1 mA VCC =2.7 to 4.0 V -IOH = 0.1 mA VCC - 2.0
--
--
V
--
--
Output low voltage
VOL
P10 to P12, P14 to P17, P20 to P22, P50 to P57, P74 to P76 P80 to P87
VCC = 4.0 to 5.5 V -- IOL = 1.6 mA IOL = 0.4 mA --
--
0.6
V
-- --
0.4 1.5 V
VCC = 4.0 to 5.5 V -- IOL = 20.0 mA VCC = 4.0 to 5.5 V -- IOL = 10.0 mA VCC = 4.0 to 5.5 V -- IOL = 1.6 mA IOL = 0.4 mA --
--
1.0
--
0.4
-- --
0.4 0.6 V
SCL, SDA
VCC = 4.0 to 5.5 V -- IOL = 6.0 mA IOL = 3.0 mA -- --
-- --
0.4 1.0 A
Input/ output leakage current
| IIL |
VIN = 0.5 V to OSC1, NMI, WKP0 to WKP5, (VCC - 0.5 V) IRQ0 to IRQ3, ADTRG, TRGV, TMRIV, TMCIV, FTCI, FTIOA to FTIOD, RXD, SCK3, SCL, SDA P10 to P12, P14 to P17, P20 to P22, P50 to P57, P74 to P76, P80 to P87 PB0 to PB7 VIN = 0.5 V to (VCC - 0.5 V)
--
--
1.0
A
VIN = 0.5 V to (AVCC - 0.5 V)
--
--
1.0
A
Rev.5.00 Nov. 02, 2005 Page 338 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics Values Item Pull-up MOS current Symbol -Ip Applicable Pins P10 to P12, P14 to P17, P50 to P55 Test Condition VCC = 5.0 V, VIN = 0.0 V VCC = 3.0 V, VIN = 0.0 V f = 1 MHz, VIN = 0.0 V, Ta = 25C Active mode 1 VCC = 5.0 V, fOSC = 20 MHz Active mode 1 VCC = 3.0 V, fOSC = 10 MHz VCC Active mode 2 VCC = 5.0 V, fOSC = 20 MHz Active mode 2 VCC = 3.0 V, fOSC = 10 MHz ISLEEP1 Sleep mode current consumption VCC Sleep mode 1 VCC = 5.0 V, fOSC = 20 MHz Sleep mode 1 VCC = 3.0 V, fOSC = 10 MHz VCC Sleep mode 2 VCC = 5.0 V, fOSC = 20 MHz Sleep mode 2 VCC = 3.0 V, fOSC = 10 MHz Subactive ISUB mode current consumption VCC VCC = 3.0 V 32-kHz crystal resonator (SUB = W/2) VCC = 3.0 V 32-kHz crystal resonator (SUB = W/8) Min 50.0 -- -- Typ -- 60.0 -- Max 300.0 -- 15.0 pF Unit A Reference value Notes
Input capacitance
Cin
All input pins except power supply pins SDA, SCL
-- --
-- 20.0
25.0 30.0
pF mA
HD6483694G
IOPE1 Active mode current consumption
VCC
*
--
8.0
--
* Reference value mA *
IOPE2
--
2.0
3.0
--
1.2
--
* Reference value mA *
--
10.0
17.5
--
5.5
--
* Reference value mA *
ISLEEP2
--
1.6
2.4
--
0.8
--
* Reference value A *
--
40.0
70.0
--
30.0
--
* Reference value
Rev.5.00 Nov. 02, 2005 Page 339 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics Values Item Symbol Applicable Pins VCC Test Condition VCC = 3.0 V 32-kHz crystal resonator (SUB = W/2) Min -- Typ 30.0 Max 50.0 Unit A Notes *
Subsleep ISUBSP mode current consumption ISTBY Standby mode current consumption RAM data VRAM retaining voltage
VCC
32-kHz crystal -- resonator not used
--
5.0
A
*
VCC
2.0
--
--
V
Note:
*
Pin states during current consumption measurement are given below (excluding current in the pull-up MOS transistors and output buffers).
RES Pin VCC Internal State Operates Other Pins VCC Oscillator Pins Main clock: ceramic or crystal resonator Subclock: Pin X1 = VSS VCC
Mode Active mode 1
Active mode 2 Sleep mode 1 Sleep mode 2 Subactive mode VCC VCC
Operates (OSC/64) Only timers operate Only timers operate (OSC/64) Operates VCC
Main clock: ceramic or crystal resonator Subclock: crystal resonator Main clock: ceramic or crystal resonator Subclock: Pin X1 = VSS
Subsleep mode Standby mode
VCC VCC
Only timers operate CPU and timers both stop
VCC VCC
Rev.5.00 Nov. 02, 2005 Page 340 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
Table 21.12 DC Characteristics (2) VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise indicated.
Values Item EEPROM current consumption Symbol IEEW IEER IEESTBY Applicable Pins VCC VCC VCC Test Condition VCC = 5.0 V, tSCL = 2.5 s (when writing) VCC = 5.0 V, tSCL = 2.5 s (when reading) VCC = 5.0 V, tSCL = 2.5 s (at standby) Min -- -- -- Typ -- -- -- Max 2.0 0.3 3.0 Unit mA mA A Notes *
Note:
*
The current consumption of the EEPROM chip is shown. For the current consumption of H8/3694N, add the above current values to the current consumption of H8/3694.
Rev.5.00 Nov. 02, 2005 Page 341 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
Table 21.12 DC Characteristics (3) VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Applicable Item Allowable output low current (per pin) Symbol Pins IOL Test Condition Min Values Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max 2.0 20.0 10.0 6.0 0.5 40.0 80.0 20.0 40.0 2.0 0.2 30.0 8.0 mA mA mA Unit mA
Output pins except port VCC = 4.0 to 5.5 V -- 8, SCL, and SDA Port 8 Port 8 SCL, and SDA Output pins except port 8, SCL, and SDA -- -- -- --
Allowable output low current (total)
IOL
Output pins except port VCC = 4.0 to 5.5 V -- 8, SCL, and SDA Port 8, SCL, and SDA Output pins except port 8, SCL, and SDA Port 8, SCL, and SDA -- -- -- VCC = 4.0 to 5.5 V -- --
Allowable output high current (per pin) Allowable output high current (total)
-IOH
All output pins
-IOH All output pins
VCC = 4.0 to 5.5 V -- --
Rev.5.00 Nov. 02, 2005 Page 342 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
21.3.3
AC Characteristics
Table 21.13 AC Characteristics VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Applicable Pins Test Condition OSC1, OSC2 VCC = 4.0 to 5.5 V Values Min 2.0 2.0 tcyc X1, X2 X1, X2 1 -- -- -- 2 2 trc OSC1, OSC2 OSC1, OSC2 X1, X2 OSC1 OSC1 OSC1 OSC1 RES VCC = 4.0 to 5.5 V VCC = 4.0 to 5.5 V VCC = 4.0 to 5.5 V VCC = 4.0 to 5.5 V -- -- -- Typ -- Max 20.0 10.0 64 12.8 tOSC s kHz s tW tcyc tsubcyc ms *
2
Item System clock oscillation frequency System clock () cycle time
Symbol fOSC
Unit MHz
Reference Figure *
1
*
2
Subclock oscillation fW frequency Watch clock (W) cycle time Subclock (SUB) cycle time Instruction cycle time Oscillation stabilization time (crystal resonator) tW tsubcyc
32.768 -- 30.5 -- -- -- -- 8 -- 10.0
Oscillation trc stabilization time (ceramic resonator) Oscillation stabilization time External clock high width External clock low width External clock rise time External clock fall time RES pin low width trcx tCPH tCPL tCPr tCPf tREL
--
--
5.0
ms
-- 20.0 40.0 20.0 40.0 -- -- -- -- At power-on and in trc modes other than those below In active mode and 200 sleep mode operation
-- -- -- -- -- -- -- -- -- --
2.0 -- -- -- -- 10.0 15.0 10.0 15.0 --
s ns ns ns ns ms Figure 21.2 Figure 21.1
--
--
ns
Rev.5.00 Nov. 02, 2005 Page 343 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics Values Test Condition Min 2 Typ -- Max -- Unit tcyc tsubcyc
Item Input pin high width
Symbol tIH
Applicable Pins NMI, IRQ0 to IRQ3, WKP0 to WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTCI, FTIOA to FTIOD NMI, IRQ0 to IRQ3, WKP0 to WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTCI, FTIOA to FTIOD
Reference Figure Figure 21.3
Input pin low width
tIL
2
--
--
tcyc tsubcyc
Notes: 1
When an external clock is input, the minimum system clock oscillation frequency is 1.0 MHz. 2. Determined by MA2, MA1, MA0, SA1, and SA0 of system control register 2 (SYSCR2).
Rev.5.00 Nov. 02, 2005 Page 344 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
Table 21.14 I2C Bus Interface Timing VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise specified.
Test Condition Min 3tcyc + 300 5tcyc + 300 -- -- Values Typ -- -- -- -- Max -- -- -- 300 1tcyc Unit ns ns ns ns ns Reference Figure Figure 21.4
Item SCL input cycle time SCL input high width SCL input low width SCL and SDA input fall time SCL and SDA input spike pulse removal time SDA input bus-free time Start condition input hold time Retransmission start condition input setup time Setup time for stop condition input Data-input hold time Capacitive load of SCL and SDA SCL and SDA output fall time
Symbol tSCL tSCLH tSCLL tSf tSP
12tcyc + 600 --
tBUF tSTAH tSTAS
5tcyc 3tcyc 3tcyc
-- -- --
-- -- --
ns ns ns
tSTOS
3tcyc 1tcyc+20 0 0 VCC = 4.0 to -- 5.5 V --
-- -- -- -- -- --
-- -- -- 400 250 300
ns ns ns pF ns
Data-input setup time tSDAS tSDAH cb tSf
Rev.5.00 Nov. 02, 2005 Page 345 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
Table 21.15 Serial Communication Interface (SCI) Timing VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise specified.
Applicable Pins Test Condition SCK3 Values Min 4 6 tSCKW tTXD SCK3 TXD VCC = 4.0 to 5.5 V 0.4 -- -- tRXS RXD VCC = 4.0 to 5.5 V 50.0 100.0 tRXH RXD VCC = 4.0 to 5.5 V 50.0 100.0 Typ -- -- -- -- -- -- -- -- -- Max Unit -- -- 0.6 1 1 -- -- -- -- ns ns tScyc tcyc Figure 21.6 tcyc Reference Figure Figure 21.5
Item Input clock cycle Asynchronous Clocked synchronous
Symbol tScyc
Input clock pulse width Transmit data delay time (clocked synchronous) Receive data setup time (clocked synchronous) Receive data hold time (clocked synchronous)
Rev.5.00 Nov. 02, 2005 Page 346 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
21.3.4
A/D Converter Characteristics
Table 21.16 A/D Converter Characteristics VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Applicable Pins AVCC AN0 to AN7 AVCC Test Condition Values Min 3.0 Typ VCC Max 5.5 Unit V Reference Figure *
1
Item
Symbol
Analog power supply AVCC voltage Analog input voltage AVIN Analog power supply AIOPE current
VSS - 0.3 -- AVCC = 5.0 V -- fOSC = 20 MHz --
AVCC + 0.3 V 2.0 mA
AISTOP1
AVCC
--
50
--
A
* Reference value *
3
2
AISTOP2 Analog input capacitance Allowable signal source impedance Resolution (data length) Conversion time (single mode) Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Conversion time (single mode) Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy CAIN RAIN
AVCC AN0 to AN7 AN0 to AN7
-- -- -- 10 AVCC = 3.0 to 134 5.5 V -- -- -- -- -- AVCC = 4.0 to 70 5.5 V -- -- -- -- --
-- -- -- 10 -- -- -- -- -- -- -- -- -- -- -- --
5.0 30.0 5.0 10 -- 7.5 7.5 7.5 0.5 8.0 -- 7.5 7.5 7.5 0.5 8.0
A pF k bit tcyc LSB LSB LSB LSB LSB tcyc LSB LSB LSB LSB LSB
Rev.5.00 Nov. 02, 2005 Page 347 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics Values Min Typ -- -- -- -- -- -- Max -- 3.5 3.5 3.5 0.5 4.0 Unit tcyc LSB LSB LSB LSB LSB
Item Conversion time (single mode) Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy
Symbol
Applicable Test Pins Condition
Reference Figure
AVCC = 4.0 to 5.5 V 134 -- -- -- -- --
Notes: 1 Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at reset and in standby, subactive, and subsleep modes while the A/D converter is idle.
21.3.5
Watchdog Timer Characteristics
Table 21.17 Watchdog Timer Characteristics VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Applicable Item On-chip oscillator overflow time Note: * Symbol tOVF Pins Test Condition Min 0.2 Values Typ 0.4 Max -- Unit s Reference Figure *
Shows the time to count from 0 to 255, at which point an internal reset is generated, when the internal oscillator is selected.
Rev.5.00 Nov. 02, 2005 Page 348 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
21.3.6
EEPROM Characteristics
Table 21.18 EEPROM Characteristics VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise indicated.
Values Test Condition Min Typ Max Unit 2500 600 1200 1200 600 600 600 160 0 50 0 100 50 300 300 400 900 10 13 ns s ns ns ns ns ns ns ns ns ns ns ns pF ns ms ms Reference Figure Figure 21.7
Item SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input spike pulse removal time SDA input bus-free time Start condition input hold time Retransmit start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA input fall time SDA input rise time Data output hold time SCL, SDA capacitive load Access time Cycle time at writing* Reset release time Note: *
Symbol tSCL tSCLH tSCLL tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH tSf tSr tDH Cb tAA tWC tRES
Cycle time at writing is a time from the stop condition to write completion (internal control).
Rev.5.00 Nov. 02, 2005 Page 349 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
21.3.7
Power-Supply-Voltage Detection Circuit Characteristics (Optional)
Table 21.19 Power-Supply-Voltage Detection Circuit Characteristics VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Test Condition LVDSEL = 0 LVDSEL = 0 LVDSEL = 0 LVDSEL = 1 Values Min 3.3 -- -- 3.0 1.0 50 LVDE = 1, Vcc = 5.0 V, When a 32kHz crystal resonator is not used -- Typ 3.7 4.0 2.3 3.6 -- -- -- Max -- 4.5 2.7 4.2 -- -- 350 Unit V V V V V s A
Item
Symbol Vint (D) Vint (U) Vreset1 Vreset2 VLVDRmin tLVDON ISTBY
Power-supply falling detection voltage Power-supply rising detection voltage Reset detection voltage 1*1 Reset detection voltage 2*2 Lower-limit voltage of LVDR 3 operation* LVD stabilization time Current consumption in standby mode
Notes: 1. This voltage should be used when the falling and rising voltage detection function is used. 2. Select the low-voltage reset 2 when only the low-voltage detection reset is used. 3. When the power-supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises, a reset may not occur. Therefore sufficient evaluation is required.
Rev.5.00 Nov. 02, 2005 Page 350 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
21.3.8
Power-On Reset Circuit Characteristics (Optional)
Table 21.20 Power-On Reset Circuit Characteristics VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Test Condition Values Min 100 -- Typ 150 -- Max -- 100 Unit k mV
Item
Symbol RRES Vpor
Pull-up resistance of RES pin Power-on reset start voltage* Note: *
The power-supply voltage (Vcc) must fall below Vpor = 100 mV and then rise after charge of the RES pin is removed completely. In order to remove charge of the RES pin, it is recommended that the diode be placed in the Vcc side. If the power-supply voltage (Vcc) rises from the point over 100 mV, a power-on reset may not occur.
21.4
Operation Timing
t OSC
VIH OSC1 VIL
t CPH t CPr
t CPL t CPf
Figure 21.1 System Clock Input Timing
Rev.5.00 Nov. 02, 2005 Page 351 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
VCC
VCC x 0.7
OSC1
tREL
RES
VIL
VIL tREL
Figure 21.2 RES Low Width Timing
NMI IRQ0 to IRQ3 WKP0 to WKP5 ADTRG FTCI FTIOA to FTIOD TMCIV, TMRIV TRGV
VIH VIL
t IL
t IH
Figure 21.3 Input Timing
SDA tBUF
VIH VIL tSTAH tSCLH tSTAS tSP tSTOS
SCL P* S* tSf tSCLL tSCL tSDAH Sr* tSDAS
P*
Note: * S, P, and Sr represent the following: S: Start condition P: Stop condition Sr: Retransmission start condition
Figure 21.4 I2C Bus Interface Input/Output Timing
Rev.5.00 Nov. 02, 2005 Page 352 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
t SCKW
SCK3
t Scyc
Figure 21.5 SCK3 Input Clock Timing
t Scyc
SCK3
VIH or VOH * VIL or VOL *
t TXD
TXD (transmit data)
VOH VOL
*
*
t RXS
t RXH
RXD (receive data)
Note:
* Output timing reference levels Output high: Output low: V OH= 2.0 V V OL= 0.8 V
Load conditions are shown in figure 21.8.
Figure 21.6 SCI Input/Output Timing in Clocked Synchronous Mode
Rev.5.00 Nov. 02, 2005 Page 353 of 418 REJ09B0028-0500
Section 21 Electrical Characteristics
tSf SCL tSTAS tSTAH SDA (in) tAA SDA (out) tSr
1/fSCL tSCLH tSCLL
tSP
tSDAH tSDAS tSTOS
tBUF
tDH
Figure 21.7 EEPROM Bus Timing
21.5
Output Load Condition
VCC
2.4 k
LSI output pin 30 pF 12 k
Figure 21.8 Output Load Circuit
Rev.5.00 Nov. 02, 2005 Page 354 of 418 REJ09B0028-0500
Appendix
Appendix A Instruction Set
A.1 Instruction List
Condition Code
Symbol Rd Rs Rn ERd ERs ERn (EAd) (EAs) PC SP CCR N Z V C disp + - x / ( ), < > Description General destination register General source register General register General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) Destination operand Source operand Program counter Stack pointer Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Displacement Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right Addition of the operands on both sides Subtraction of the operand on the right from the operand on the left Multiplication of the operands on both sides Division of the operand on the left by the operand on the right Logical AND of the operands on both sides Logical OR of the operands on both sides Logical exclusive OR of the operands on both sides NOT (logical complement) Contents of operand
Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers (R0 to R7 and E0 to E7).
Rev.5.00 Nov. 02, 2005 Page 355 of 418 REJ09B0028-0500
Appendix
Condition Code Notation (cont)
Symbol Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1 Not affected by execution of the instruction Varies depending on conditions, described in notes
Rev.5.00 Nov. 02, 2005 Page 356 of 418 REJ09B0028-0500
* 0 1 --
Appendix
Table A.1
Instruction Set
1. Data Transfer Instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
Condition Code
No. of States*1
@(d, ERn)
I
H
N
Z
V
C
MOV MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd
B B B B B B
2 2 2 4 8 2
---- ---- ---- ---- ---- ----
#xx:8 Rd8 Rs8 Rd8 @ERs Rd8 @(d:16, ERs) Rd8 @(d:24, ERs) Rd8 @ERs Rd8 ERs32+1 ERs32 2 4 6 2 4 8 2 @aa:8 Rd8 @aa:16 Rd8 @aa:24 Rd8 Rs8 @ERd Rs8 @(d:16, ERd) Rs8 @(d:24, ERd) ERd32-1 ERd32 Rs8 @ERd 2 4 6 Rs8 @aa:8 Rs8 @aa:16 Rs8 @aa:24 #xx:16 Rd16 2 2 4 8 2 Rs16 Rd16 @ERs Rd16 @(d:16, ERs) Rd16 @(d:24, ERs) Rd16 @ERs Rd16 ERs32+2 @ERd32 4 6 2 4 8 @aa:16 Rd16 @aa:24 Rd16 Rs16 @ERd Rs16 @(d:16, ERd) Rs16 @(d:24, ERd)
0-- 0-- 0-- 0-- 0-- 0--
2 2 4 6 10 6
MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @ERd MOV.B Rs, @(d:16, ERd) MOV.B Rs, @(d:24, ERd) MOV.B Rs, @-ERd
B B B B B B B
---- ---- ---- ---- ---- ---- ----
0-- 0-- 0-- 0-- 0-- 0-- 0--
4 6 8 4 6 10 6
MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd
B B B W4 W W
---- ---- ---- ---- ---- ---- ---- ---- ----
0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0--
4 6 8 4 2 4 6 10 6
MOV.W @(d:16, ERs), Rd W MOV.W @(d:24, ERs), Rd W MOV.W @ERs+, Rd W
MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd
W W W
---- ---- ---- ---- ----
0-- 0-- 0-- 0-- 0--
6 8 4 6 10
MOV.W Rs, @(d:16, ERd) W MOV.W Rs, @(d:24, ERd) W
Rev.5.00 Nov. 02, 2005 Page 357 of 418 REJ09B0028-0500
Advanced
Mnemonic
Operation
@(d, PC) Normal @@aa
@ERn
@aa
#xx
Rn
--
Appendix
Addressing Mode and Instruction Length (bytes)
No. of States*1
Condition Code
@(d, ERn)
I
H
N
Z
V
C
MOV MOV.W Rs, @-ERd MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 MOV.L #xx:32, Rd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16, ERs), ERd MOV.L @(d:24, ERs), ERd MOV.L @ERs+, ERd
W
2
ERd32-2 ERd32 Rs16 @ERd 4 6 Rs16 @aa:16 Rs16 @aa:24 #xx:32 Rd32 ERs32 ERd32
----
0--
6
W W L L L L L L 6 2 4 6 10 4
---- ---- ---- ---- ---- ---- ---- ----
0-- 0-- 0-- 0-- 0-- 0-- 0-- 0--
6 8 6 2 8 10 14 10
@ERs ERd32 @(d:16, ERs) ERd32 @(d:24, ERs) ERd32 @ERs ERd32 ERs32+4 ERs32 6 8 @aa:16 ERd32 @aa:24 ERd32 ERs32 @ERd 6 10 4 ERs32 @(d:16, ERd) ERs32 @(d:24, ERd) ERd32-4 ERd32 ERs32 @ERd 6 8 ERs32 @aa:16 ERs32 @aa:24 2 @SP Rn16 SP+2 SP 4 @SP ERn32 SP+4 SP 2 SP-2 SP Rn16 @SP 4 SP-4 SP ERn32 @SP 4 Cannot be used in this LSI Cannot be used in this LSI
MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs, @ERd MOV.L ERs, @(d:16, ERd) MOV.L ERs, @(d:24, ERd) MOV.L ERs, @-ERd
L L L L L L 4
---- ---- ---- ---- ---- ----
0-- 0-- 0-- 0-- 0-- 0--
10 12 8 10 14 10
MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 POP POP.W Rn POP.L ERn
L L W
---- ---- ----
0-- 0-- 0--
10 12 6
L
----
0--
10
PUSH PUSH.W Rn PUSH.L ERn
W
----
0--
6
L
----
0--
10
MOVFPE
MOVFPE @aa:16, Rd
B
Cannot be used in this LSI Cannot be used in this LSI
MOVTPE
MOVTPE Rs, @aa:16
B
4
Rev.5.00 Nov. 02, 2005 Page 358 of 418 REJ09B0028-0500
Advanced
Mnemonic
@-ERn/@ERn+
Operand Size
Operation
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
Appendix
2. Arithmetic Instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
Condition Code
@(d, ERn)
I
H
N
Z
V
C

ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd
B B
2 2
-- --
Rd8+#xx:8 Rd8 Rd8+Rs8 Rd8 Rd16+#xx:16 Rd16 2 Rd16+Rs16 Rd16 ERd32+#xx:32 ERd32 2 ERd32+ERs32 ERd32 Rd8+#xx:8 +C Rd8 2 2 2 2 2 2 2 2 2 2 Rd8+Rs8 +C Rd8 ERd32+1 ERd32 ERd32+2 ERd32 ERd32+4 ERd32 Rd8+1 Rd8 Rd16+1 Rd16 Rd16+2 Rd16 ERd32+1 ERd32 ERd32+2 ERd32 Rd8 decimal adjust Rd8 Rd8-Rs8 Rd8 Rd16-#xx:16 Rd16 2 Rd16-Rs16 Rd16
2 2 4 2 6
W4 W L 6
-- (1) -- (1) -- (2)
ADD.L ERs, ERd
L
-- (2)
2
ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd ADDS ADDS.L #1, ERd ADDS.L #2, ERd ADDS.L #4, ERd INC INC.B Rd INC.W #1, Rd INC.W #2, Rd INC.L #1, ERd INC.L #2, ERd DAA SUB DAA Rd
B B L L L B W W L L B
2
-- --
(3) (3)
2 2 2 2 2 2 2 2 2 2 2
------------ ------------ ------------
---- ---- ---- ---- ---- --*
-- -- -- -- --
*--
SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd SUB.L ERs, ERd
B W4 W L L B B L L L B W W 2 6
2
--
2 4 2 6 2 2 2 2 2 2 2 2 2
-- (1) -- (1)
ERd32-#xx:32 ERd32 -- (2) 2 ERd32-ERs32 ERd32 -- (2)
SUBX SUBX.B #xx:8, Rd SUBX.B Rs, Rd SUBS SUBS.L #1, ERd SUBS.L #2, ERd SUBS.L #4, ERd
DEC DEC.B Rd
Rd8-#xx:8-C Rd8 2 2 2 2 2 2 2 Rd8-Rs8-C Rd8 ERd32-1 ERd32 ERd32-2 ERd32 ERd32-4 ERd32 Rd8-1 Rd8 Rd16-1 Rd16 Rd16-2 Rd16
-- --
(3) (3)
------------ ------------ ------------
---- ---- ----
-- -- --
DEC.W #1, Rd DEC.W #2, Rd
Rev.5.00 Nov. 02, 2005 Page 359 of 418 REJ09B0028-0500
Advanced
Mnemonic
@-ERn/@ERn+
Operand Size
Operation
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
Appendix
Addressing Mode and Instruction Length (bytes)
No. of States*1
Condition Code
@(d, ERn)
I
H
N
Z
V
C
DEC DEC.L #1, ERd DEC.L #2, ERd DAS DAS.Rd
L L B
2 2 2
---- ---- --*
ERd32-1 ERd32 ERd32-2 ERd32 Rd8 decimal adjust Rd8 Rd8 x Rs8 Rd16 (unsigned multiplication) Rd16 x Rs16 ERd32 (unsigned multiplication) Rd8 x Rs8 Rd16 (signed multiplication) Rd16 x Rs16 ERd32 (signed multiplication) Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (unsigned division) ERd32 / Rs16 ERd32 (Ed: remainder, Rd: quotient) (unsigned division) Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (signed division) ERd32 / Rs16 ERd32 (Ed: remainder, Rd: quotient) (signed division) Rd8-#xx:8
-- --
2 2 2
*--
MULXU MULXU. B Rs, Rd
B
2
------------
14
MULXU. W Rs, ERd
W
2
------------
22
MULXS MULXS. B Rs, Rd
B
4
----
----
16
MULXS. W Rs, ERd
W
4
----
----
24
DIVXU DIVXU. B Rs, Rd
B
2
-- -- (6) (7) -- --
14
DIVXU. W Rs, ERd
W
2
-- -- (6) (7) -- --
22
DIVXS DIVXS. B Rs, Rd
B
4
-- -- (8) (7) -- --
16
DIVXS. W Rs, ERd
W
4
-- -- (8) (7) -- --
24

CMP CMP.B #xx:8, Rd
B B
2 2
-- --
2 2 4 2 4 2
CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd
Rd8-Rs8 Rd16-#xx:16
W4 W L L 6 2 2
-- (1) -- (1) -- (2) -- (2)
Rd16-Rs16 ERd32-#xx:32 ERd32-ERs32
Rev.5.00 Nov. 02, 2005 Page 360 of 418 REJ09B0028-0500
Advanced
Mnemonic
@-ERn/@ERn+
Operand Size
Operation
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
Appendix
Addressing Mode and Instruction Length (bytes)
No. of States*1
Condition Code
@(d, ERn)
I
H
N
Z
V
C

NEG NEG.B Rd NEG.W Rd NEG.L ERd EXTU EXTU.W Rd EXTU.L ERd
B W L W
2 2 2 2
-- -- --
0-Rd8 Rd8 0-Rd16 Rd16 0-ERd32 ERd32 0 ( of Rd16) 0 ( of ERd32) ( of Rd16) ( of Rd16) ( of ERd32) ( of ERd32)
2 2 2 2
---- 0
0--
L
2
---- 0
0--
2
EXTS EXTS.W Rd
W
2
----
0--
2
EXTS.L ERd
L
2
----
0--
2
Rev.5.00 Nov. 02, 2005 Page 361 of 418 REJ09B0028-0500
Advanced
Mnemonic
@-ERn/@ERn+
Operand Size
Operation
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
Appendix
3. Logic Instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
Condition Code
@(d, ERn)
I
H
N
Z
V
C
AND
AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd
B B
2 2
---- ---- ---- ----
Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 2 Rd16Rs16 Rd16
0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0--
2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2
W4 W L L B B W4 W L L B B W4 W L L B W L 6 4 2 2 2 2 2 2 6 4 2 2 2 6 4
ERd32#xx:32 ERd32 -- -- ERd32ERs32 ERd32 -- -- Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 Rd16Rs16 Rd16 ERd32#xx:32 ERd32 ERd32ERs32 ERd32 Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 Rd16Rs16 Rd16 ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
OR
OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd
XOR
XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd
ERd32#xx:32 ERd32 -- -- ERd32ERs32 ERd32 -- -- Rd8 Rd8 Rd16 Rd16 Rd32 Rd32 ---- ---- ----
NOT
NOT.B Rd NOT.W Rd NOT.L ERd
Rev.5.00 Nov. 02, 2005 Page 362 of 418 REJ09B0028-0500
Advanced
Mnemonic
@-ERn/@ERn+
Operand Size
Operation
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
Appendix
4. Shift Instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
Condition Code
No. of States*1
@(d, ERn)
I
H
N
Z
V
C
SHAL SHAL.B Rd
B W L B W L B W L B W L B W L B W L B W L B W L
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
SHAL.W Rd SHAL.L ERd
SHAR SHAR.B Rd
C
0 MSB LSB
C
---- ---- ---- ---- ---- ---- ----
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SHAR.W Rd SHAR.L ERd
SHLL SHLL.B Rd
MSB
LSB
SHLL.W Rd SHLL.L ERd
SHLR SHLR.B Rd
C
0 MSB LSB
C MSB
LSB
---- ---- ----
SHLR.W Rd SHLR.L ERd
ROTXL ROTXL.B Rd
0
---- ---- ----
ROTXL.W Rd ROTXL.L ERd
ROTXR ROTXR.B Rd
C MSB
LSB
C MSB
C MSB
LSB
C MSB
LSB
---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
LSB
ROTXR.W Rd ROTXR.L ERd
ROTL ROTL.B Rd
ROTL.W Rd ROTL.L ERd
ROTR ROTR.B Rd
ROTR.W Rd ROTR.L ERd
Rev.5.00 Nov. 02, 2005 Page 363 of 418 REJ09B0028-0500
Advanced
Mnemonic
Operation
@(d, PC) Normal @@aa
@ERn
@aa
#xx
Rn
--
Appendix
5. Bit-Manipulation Instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
Condition Code
No. of States*1
@(d, ERn)
I
H
N
Z
V
C
BSET BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BCLR BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 BNOT BNOT #xx:3, Rd
B B B B B B B B B B B B B
2 4 4 2 4 4 2 4 4 2 4 4 2
(#xx:3 of Rd8) 1 (#xx:3 of @ERd) 1 (#xx:3 of @aa:8) 1 (Rn8 of Rd8) 1 (Rn8 of @ERd) 1 (Rn8 of @aa:8) 1 (#xx:3 of Rd8) 0 (#xx:3 of @ERd) 0 (#xx:3 of @aa:8) 0 (Rn8 of Rd8) 0 (Rn8 of @ERd) 0 (Rn8 of @aa:8) 0 (#xx:3 of Rd8) (#xx:3 of Rd8) 4 (#xx:3 of @ERd) (#xx:3 of @ERd) 4 (#xx:3 of @aa:8) (#xx:3 of @aa:8) (Rn8 of Rd8) (Rn8 of Rd8) 4 (Rn8 of @ERd) (Rn8 of @ERd) 4 (Rn8 of @aa:8) (Rn8 of @aa:8) (#xx:3 of Rd8) Z 4 4 (#xx:3 of @ERd) Z (#xx:3 of @aa:8) Z (Rn8 of @Rd8) Z 4 4 (Rn8 of @ERd) Z (Rn8 of @aa:8) Z (#xx:3 of Rd8) C
------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------
2 8 8 2 8 8 2 8 8 2 8 8 2
BNOT #xx:3, @ERd
B
------------
8
BNOT #xx:3, @aa:8
B
------------
8
BNOT Rn, Rd
B
2
------------
2
BNOT Rn, @ERd
B
------------
8
BNOT Rn, @aa:8
B
------------
8
BTST BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BLD BLD #xx:3, Rd
B B B B B B B
2
------ ------ ------ ------ ------ ------
---- ---- ---- ---- ---- ----
2 6 6 2 6 6 2
2
2
----------
Rev.5.00 Nov. 02, 2005 Page 364 of 418 REJ09B0028-0500
Advanced
Mnemonic
Operation
@(d, PC) Normal @@aa
@ERn
@aa
#xx
Rn
--
Appendix
Addressing Mode and Instruction Length (bytes)
No. of States*1
Condition Code
@(d, ERn)
I
H
N
Z
V
C
BLD
BLD #xx:3, @ERd BLD #xx:3, @aa:8
B B B B B B B B B B B B B B B B B B B B B B B B B B B B B 2 2 2 2 2 2 2 2 2
4 4
---------- ---------- ---------- ---------- ----------
(#xx:3 of @ERd) C (#xx:3 of @aa:8) C (#xx:3 of Rd8) C (#xx:3 of @ERd) C 4 (#xx:3 of @aa:8) C C (#xx:3 of Rd8) C (#xx:3 of @ERd24) 4 C (#xx:3 of @aa:8) C (#xx:3 of Rd8) C (#xx:3 of @ERd24) 4 C (#xx:3 of @aa:8) C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C 4 C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C C (#xx:3 of @ERd24) C 4 C (#xx:3 of @aa:8) C C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C 4 C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C C (#xx:3 of @ERd24) C 4 C (#xx:3 of @aa:8) C C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C 4 C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C
6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6
BILD BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8 BST BST #xx:3, Rd BST #xx:3, @ERd BST #xx:3, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BAND BAND #xx:3, Rd BAND #xx:3, @ERd BAND #xx:3, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @ERd BIAND #xx:3, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BIOR BIOR #xx:3, Rd BIOR #xx:3, @ERd BIOR #xx:3, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8
BIXOR BIXOR #xx:3, Rd
4
------------ ------------ ------------ ------------ ------------ ------------ ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ----------
4
4
4
4
4
4
4
BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8
4 4
C (#xx:3 of @ERd24) C -- -- -- -- -- C (#xx:3 of @aa:8) C ----------
Rev.5.00 Nov. 02, 2005 Page 365 of 418 REJ09B0028-0500
Advanced
Mnemonic
@-ERn/@ERn+
Operand Size
Operation
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
Appendix
6. Branching Instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
Condition Code
No. of States*1
@(d, ERn)
Branch Condition If condition Always is true then PC PC+d Never else next; C Z = 0
I
H
N
Z
V
C
Bcc
BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4
------------ ------------ ------------ ------------ ------------ ------------
4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6
C Z = 1
------------ ------------
C=0
------------ ------------
C=1
------------ ------------
Z=0
------------ ------------
Z=1
------------ ------------
V=0
------------ ------------
V=1
------------ ------------
N=0
------------ ------------
N=1
------------ ------------
NV = 0
------------ ------------
NV = 1
------------ ------------
Z (NV) = 0 -- -- -- -- -- -- ------------ Z (NV) = 1 -- -- -- -- -- -- ------------
Rev.5.00 Nov. 02, 2005 Page 366 of 418 REJ09B0028-0500
Advanced
Mnemonic
Operation
@(d, PC) Normal @@aa
@ERn
@aa
#xx
Rn
--
Appendix
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
Condition Code
No. of States*1
@(d, ERn)
I
H
N
Z
V
C
JMP
JMP @ERn JMP @aa:24 JMP @@aa:8
-- -- -- --
2 4 2 2
PC ERn PC aa:24 PC @aa:8 PC @-SP PC PC+d:8 PC @-SP PC PC+d:16 PC @-SP PC ERn 4 PC @-SP PC aa:24 2 PC @-SP PC @aa:8 2 PC @SP+
------------ ------------ ------------ ------------
8 6
4 6
10 8
BSR
BSR d:8
BSR d:16
JSR
--
4
------------
8
10
JSR @ERn
--
2
------------
6
JSR @aa:24
--
------------
8
10
JSR @@aa:8
--
------------
8
12
RTS
RTS
--
------------
8
10
Rev.5.00 Nov. 02, 2005 Page 367 of 418 REJ09B0028-0500
Advanced
Mnemonic
Operation
@(d, PC) Normal @@aa
@ERn
@aa
#xx
Rn
--
8
Appendix
7. System Control Instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
Condition Code
No. of States*1
@(d, ERn)
I
H
N
Z
V
C
TRAPA TRAPA #x:2
--
2 PC @-SP CCR @-SP PC CCR @SP+ PC @SP+ Transition to powerdown state 2 2 4 6 10 4 #xx:8 CCR Rs8 CCR @ERs CCR @(d:16, ERs) CCR @(d:24, ERs) CCR @ERs CCR ERs32+2 ERs32 6 8 2 4 6 10 4 @aa:16 CCR @aa:24 CCR CCR Rd8 CCR @ERd CCR @(d:16, ERd) CCR @(d:24, ERd) ERd32-2 ERd32 CCR @ERd 6 8 2 2 2 CCR @aa:16 CCR @aa:24 CCR#xx:8 CCR CCR#xx:8 CCR CCR#xx:8 CCR 2 PC PC+2
1 -- -- -- -- -- 14
16

RTE
RTE
--
10
SLEEP SLEEP
--
------------

2
LDC
LDC #xx:8, CCR LDC Rs, CCR LDC @ERs, CCR LDC @(d:16, ERs), CCR LDC @(d:24, ERs), CCR LDC @ERs+, CCR
B B W W W W
2 2 6 8 12 8

LDC @aa:16, CCR LDC @aa:24, CCR STC STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16, ERd) STC CCR, @(d:24, ERd) STC CCR, @-ERd
W W B W W W W
8 10 2 6 8 12 8
------------ ------------ ------------ ------------ ------------ ------------ ------------

STC CCR, @aa:16 STC CCR, @aa:24 ANDC ANDC #xx:8, CCR ORC NOP ORC #xx:8, CCR XORC XORC #xx:8, CCR NOP
W W B B B --
8 10 2 2 2 2
------------
Rev.5.00 Nov. 02, 2005 Page 368 of 418 REJ09B0028-0500
Advanced
Mnemonic
Operation
@(d, PC) Normal @@aa
@ERn
@aa
#xx
Rn
--
Appendix
8. Block Transfer Instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
Condition Code
@-ERn/@ERn+
Operand Size
@(d, ERn)
I
H
N
Z
V
C
EEPMOV
EEPMOV. B
--
4 if R4L 0 then repeat @R5 @R6 R5+1 R5 R6+1 R6 R4L-1 R4L until R4L=0 else next 4 if R4 0 then repeat @R5 @R6 R5+1 R5 R6+1 R6 R4-1 R4 until R4=0 else next
-- -- -- -- -- -- 8+ 4n*2
EEPMOV. W
--
-- -- -- -- -- -- 8+ 4n*2
Notes: 1. The number of states in cases where the instruction code and its operands are located in on-chip memory is shown here. For other cases see appendix A.3, Number of Execution States. 2. n is the value set in register R4L or R4. (1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. (2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. (3) Retains its previous value when the result is zero; otherwise cleared to 0. (4) Set to 1 when the adjustment produces a carry; otherwise retains its previous value. (5) The number of states required for execution of an instruction that transfers data in synchronization with the E clock is variable. (6) Set to 1 when the divisor is negative; otherwise cleared to 0. (7) Set to 1 when the divisor is zero; otherwise cleared to 0. (8) Set to 1 when the quotient is negative; otherwise cleared to 0.
Rev.5.00 Nov. 02, 2005 Page 369 of 418 REJ09B0028-0500
Advanced
Mnemonic
Operation
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
A.2
Appendix
Table A.2
Instruction code:
REJ09B0028-0500
1st byte 2nd byte AH AL BH BL
Instruction when most significant bit of BH is 0. Instruction when most significant bit of BH is 1.
4 5 XORC
ADD SUB Table A-2 Table A-2 (2) (2)
CMP
AL 3 LDC ORC OR.B XOR.B AND.B
Table A-2 (2)
AH ANDC SUBX LDC
Table A-2 Table A-2 (2) (2)
MOV
0 ADDX
1
2
6
7
8
9
A
B
C
D
E
F
Table A-2 (2) Table A-2 (2)
0
NOP
Table A-2 (2)
STC
1
Table A-2 Table A-2 Table A-2 Table A-2 (2) (2) (2) (2)
2
MOV.B
Operation Code Map
Rev.5.00 Nov. 02, 2005 Page 370 of 418
Operation Code Map (1)
3 BLS BCC RTS BST OR BTST BOR MOV BIOR
ADD ADDX CMP SUBX OR XOR AND MOV
4 BCS BSR XOR BXOR BIXOR BIAND BILD BAND BIST BLD AND RTE TRAPA
Table A-2 (2)
BRA BNE JMP MOV
Table A-2 Table A-2 EEPMOV (2) (2)
BRN BEQ BVC BPL BMI DIVXU
BHI
BVS
BGE BSR
BLT
BGT JSR
BLE
5
MULXU
DIVXU
MULXU
6
BSET
BNOT
BCLR
7
Table A-2 (3)
8
9
A
B
C
D
E
F
Table A.2
Instruction code:
1st byte 2nd byte AH AL BH BL
2 LDC/STC SLEEP ADD INC ADDS MOV SHLL SHAL SHAR ROTL ROTR EXTU EXTU NEG SHLR ROTXL ROTXR NOT SHAL SHAR ROTL ROTR NEG SUB DEC DEC SUB CMP BHI BLS SUB SUB OR OR CMP CMP BCC BCS XOR XOR BNE AND AND BEQ BVC BVS BPL BMI BGE BLT BGT BLE DEC DEC EXTS EXTS INC INC INC Table A-2 Table A-2 (3) (3) 3 4 5 6 7 8 9 A B C D E F Table A-2 (3)
BH AH AL
0
1
01
MOV
0A
INC
0B
ADDS
Operation Code Map (2)
0F
DAA
10
SHLL
11
SHLR
12
ROTXL
13
ROTXR
17
NOT
1A
DEC
1B
SUBS
1F
DAS
58
BRA
BRN
79
MOV
ADD
7A
MOV
ADD
Appendix
Rev.5.00 Nov. 02, 2005 Page 371 of 418
REJ09B0028-0500
Appendix
Table A.2
REJ09B0028-0500
Instruction code:
1st byte 2nd byte 3rd byte 4th byte AH AL BH BL CH CL DH DL
Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1.
CL 2 3 4 5 6 7 8 9 A B C D E F
AH ALBH BLCH LDC STC STC MULXS DIVXS OR AND BTST BOR BTST BIOR BCLR BIST BCLR BTST BOR BTST BIOR BCLR BIST BCLR BIXOR BIAND BILD BST BXOR BAND BLD BIXOR BIAND BILD BST BXOR BAND BLD XOR LDC LDC
0
1
01406
STC
LDC STC
Rev.5.00 Nov. 02, 2005 Page 372 of 418
Operation Code Map (3)
01C05
MULXS
01D05
DIVXS
01F06
7Cr06 * 1
7Cr07 * 1
7Dr06 * 1
BSET
BNOT
7Dr07 * 1
BSET
BNOT
7Eaa6 * 2
7Eaa7 * 2
7Faa6 * 2
BSET
BNOT
7Faa7 * 2
BSET
BNOT
Notes: 1. r is the register designation field. 2. aa is the absolute address field.
Appendix
A.3
Number of Execution States
The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. Table A.3 shows the number of states required for each cycle. The total number of states required for execution of an instruction can be calculated by the following expression:
Execution states = I x SI + J x SJ + K x SK + L x SL + M x SM + N x SN
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed. BSET #0, @FF00 From table A.4: I = L = 2, J = K = M = N= 0 From table A.3: SI = 2, SL = 2 Number of states required for execution = 2 x 2 + 2 x 2 = 8 When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and on-chip RAM is used for stack area. JSR @@ 30 From table A.4: I = 2, J = K = 1, From table A.3: SI = SJ = SK = 2 Number of states required for execution = 2 x 2 + 1 x 2+ 1 x 2 = 8
L=M=N=0
Rev.5.00 Nov. 02, 2005 Page 373 of 418 REJ09B0028-0500
Appendix
Table A.3
Number of Cycles in Each Instruction
Access Location On-Chip Memory SI SJ SK SL SM SN 2 or 3* 2 or 3* 1 2 On-Chip Peripheral Module --
Execution Status (Instruction Cycle) Instruction fetch Branch address read Stack operation Byte data access Word data access Internal operation Note: *
Depends on which on-chip peripheral module is accessed. See section 20.1, Register Addresses (Address Order).
Rev.5.00 Nov. 02, 2005 Page 374 of 418 REJ09B0028-0500
Appendix
Table A.4
Number of Cycles in Each Instruction
Instruction Fetch Branch J Stack K Byte Data Access L Word Data Access M Internal Operation N Addr. Read Operation
Instruction Mnemonic ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS ADDX ADDS #1/2/4, ERd ADDX #xx:8, Rd ADDX Rs, Rd AND AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd ANDC BAND ANDC #xx:8, CCR BAND #xx:3, Rd BAND #xx:3, @ERd BAND #xx:3, @aa:8 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8
I 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 1
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Appendix
Instruction Fetch Instruction Mnemonic Bcc BLT d:8 BGT d:8 BLE d:8 BRA d:16(BT d:16) BRN d:16(BF d:16) BHI d:16 BLS d:16 BCC d:16(BHS d:16) BCS d:16(BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @ERd BIAND #xx:3, @aa:8 BILD BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8 I 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 1 2 2 1 2 2 1 2 2
Branch J
Stack K
Byte Data Access L
Word Data Access M
Internal Operation N
Addr. Read Operation
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2
2 2
1 1
1 1
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Appendix
Instruction Fetch Instruction Mnemonic BIOR BIOR #xx:8, Rd BIOR #xx:8, @ERd BIOR #xx:8, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8 BLD BLD #xx:3, Rd BLD #xx:3, @ERd BLD #xx:3, @aa:8 BNOT BNOT #xx:3, Rd BNOT #xx:3, @ERd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @ERd BNOT Rn, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BSET BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BSR BSR d:8 BSR d:16 BST BST #xx:3, Rd BST #xx:3, @ERd BST #xx:3, @aa:8 I 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 2 1 2 2
Branch J
Stack K
Byte Data Access L
Word Data Access M
Internal Operation N
Addr. Read Operation
1 1
2 2
1 1
1 1
2 2
2 2
1 1
2 2
2 2 1 1 2
2 2
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Appendix
Instruction Fetch Instruction Mnemonic BTST BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 CMP CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd DAA DAS DEC DAA Rd DAS Rd DEC.B Rd DEC.W #1/2, Rd DEC.L #1/2, ERd DUVXS DIVXS.B Rs, Rd DIVXS.W Rs, ERd DIVXU DIVXU.B Rs, Rd DIVXU.W Rs, ERd EEPMOV EEPMOV.B EEPMOV.W EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd I 1 2 2 1 2 2 1 2 2 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 2 2 1 1 1 1
Branch J
Stack K
Byte Data Access L
Word Data Access M
Internal Operation N
Addr. Read Operation
1 1
1 1
1 1
12 20 12 20 2n+2*
1
2n+2*1
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Appendix
Instruction Fetch Instruction Mnemonic INC INC.B Rd INC.W #1/2, Rd INC.L #1/2, ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 LDC LDC #xx:8, CCR LDC Rs, CCR LDC@ERs, CCR LDC@(d:16, ERs), CCR LDC@(d:24,ERs), CCR LDC@ERs+, CCR LDC@aa:16, CCR LDC@aa:24, CCR MOV MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @Erd MOV.B Rs, @(d:16, ERd) MOV.B Rs, @(d:24, ERd) MOV.B Rs, @-ERd MOV.B Rs, @aa:8 I 1 1 1 2 2 2 2 2 2 1 1 2 3 5 2 3 4 1 1 1 2 4 1 1 2 3 1 2 4 1 1
Branch J
Stack K
Byte Data Access L
Word Data Access M
Internal Operation N
Addr. Read Operation
2 1 1 1 1 1 2 2
1 1 1 1 1 1 2
1 1 1 1 1 1 1 1 1 1 1 1 2 2
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Appendix
Instruction Fetch Instruction Mnemonic MOV MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd MOV.W @(d:16,ERs), Rd MOV.W @(d:24,ERs), Rd MOV.W @ERs+, Rd MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd MOV.W Rs, @(d:16,ERd) MOV.W Rs, @(d:24,ERd) MOV MOV.W Rs, @-ERd MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 MOV.L #xx:32, ERd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16,ERs), ERd MOV.L @(d:24,ERs), ERd MOV.L @ERs+, ERd MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs,@ERd MOV.L ERs, @(d:16,ERd) MOV.L ERs, @(d:24,ERd) MOV.L ERs, @-ERd MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 MOVFPE MOVTPE MOVFPE @aa:16, Rd*2 MOVTPE Rs,@aa:16*2 I 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 2 2
Branch J
Stack K
Byte Data Access L 1 1
Word Data Access M
Internal Operation N
Addr. Read Operation
1 1 1 1 1 1 1 1 1 1 1 1 2 2
2 2 2 2 2 2 2 2 2 2 2 2 1 1 2 2
Rev.5.00 Nov. 02, 2005 Page 380 of 418 REJ09B0028-0500
Appendix
Instruction Fetch Instruction Mnemonic MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd MULXU MULXU.B Rs, Rd MULXU.W Rs, ERd NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOP NOT.B Rd NOT.W Rd NOT.L ERd OR OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd ORC POP ORC #xx:8, CCR POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR ROTR.B Rd ROTR.W Rd ROTR.L ERd ROTXL ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd I 2 2 1 1 1 1 1 1 1 1 1 1 1 2 1 3 2 1 1 2 1 2 1 1 1 1 1 1 1 1 1
Branch J
Stack K
Byte Data Access L
Word Data Access M
Internal Operation N 12 20 12 20
Addr. Read Operation
1 2 1 2
2 2 2 2
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Appendix
Instruction Fetch Instruction Mnemonic ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd RTE RTS SHAL RTE RTS SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR SHLR.B Rd SHLR.W Rd SHLR.L ERd SLEEP STC SLEEP STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16,ERd) STC CCR, @(d:24,ERd) STC CCR,@-ERd STC CCR, @aa:16 STC CCR, @aa:24 SUB SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd SUB.L ERs, ERd SUBS SUBS #1/2/4, ERd I 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 5 2 3 4 1 2 1 3 1 1
Branch J
Stack K
Byte Data Access L
Word Data Access M
Internal Operation N
Addr. Read Operation
2 1
2 2
1 1 1 1 1 1 2
Rev.5.00 Nov. 02, 2005 Page 382 of 418 REJ09B0028-0500
Appendix
Instruction Fetch Instruction Mnemonic SUBX SUBX #xx:8, Rd SUBX. Rs, Rd TRAPA XOR TRAPA #xx:2 XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd XORC XORC #xx:8, CCR I 1 1 2 1 1 2 1 3 2 1
Branch J
Stack K
Byte Data Access L
Word Data Access M
Internal Operation N
Addr. Read Operation
1
2
4
Notes: 1. n: Specified value in R4L. The source and destination operands are accessed n+1 times respectively. 2. It can not be used in this LSI.
Rev.5.00 Nov. 02, 2005 Page 383 of 418 REJ09B0028-0500
Appendix
A.4
Combinations of Instructions and Addressing Modes
Combinations of Instructions and Addressing Modes
Addressing Mode
@ERn+/@ERn @(d:16.ERn) @(d:24.ERn) @(d:16.PC)
Table A.5
@@aa:8
Functions
Instructions
@ERn #xx
@(d:8.PC)
@aa:16
@aa:24
@aa:8
Rn
Data MOV transfer POP, PUSH instructions MOVFPE, MOVTPE ADD, CMP Arithmetic operations SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, MULXS, DIVXU, DIVXS NEG EXTU, EXTS AND, OR, XOR Logical operations NOT Shift operations Bit manipulations BCC, BSR Branching instructions JMP, JSR RTS TRAPA System control RTE instructions SLEEP LDC STC ANDC, ORC, XORC NOP Block data transfer instructions
BWL BWL BWL BWL BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- BWL WL B -- -- -- -- BWL BWL B L BWL B BW -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
B -- -- -- -- -- -- -- -- --
BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
-- WL -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- B -- B -- --
BWL WL BWL BWL BWL B -- -- -- -- -- -- B B -- -- --
-- -- -- -- -- B -- -- -- -- -- W W -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- W W -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- W W -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- W W -- -- --
-- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- W W -- -- --
-- -- -- -- -- -- -- -- -- -- -- W W -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- --
-- --
BW
Rev.5.00 Nov. 02, 2005 Page 384 of 418 REJ09B0028-0500
--
Appendix
Appendix B I/O Port Block Diagrams
B.1 I/O Port Block Diagrams
RES goes low in a reset, and SBY goes low in a reset and in standby mode.
Internal data bus
RES
SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
IRQ TRGV [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.1 Port 1 Block Diagram (P17)
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Appendix
Internal data bus
RES PUCR
SBY
Pull-up MOS PMR
PDR
PCR
IRQ [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.2 Port 1 Block Diagram (P16 to P14)
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Appendix
Internal data bus
RES PUCR
SBY
Pull-up MOS
PDR
PCR
[Legend] PUCR: Port pull-up control register PDR: Port data register PCR: Port control register
Figure B.3 Port 1 Block Diagram (P12, P11)
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Appendix
Internal data bus
RES PUCR
SBY
Pull-up MOS PMR
PDR
PCR
Timer A TMOW [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.4 Port 1 Block Diagram (P10)
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Appendix
Internal data bus
SBY
PMR
PDR
PCR
SCI3 TxD [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.5 Port 2 Block Diagram (P22)
Rev.5.00 Nov. 02, 2005 Page 389 of 418 REJ09B0028-0500
Appendix
Internal data bus
SBY
PDR
PCR
SCI3 RE RxD [Legend] PDR: Port data register PCR: Port control register
Figure B.6 Port 2 Block Diagram (P21)
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Appendix
SBY SCI3 SCKIE SCKOE Internal data bus PDR
PCR
SCKO SCKI [Legend] PDR: Port data register PCR: Port control register
Figure B.7 Port 2 Block Diagram (P20)
Rev.5.00 Nov. 02, 2005 Page 391 of 418 REJ09B0028-0500
Appendix
Internal data bus
SBY
PDR
PCR
IIC2 ICE SDAO/SCLO SDAI/SCLI
[Legend] PDR: Port data register PCR: Port control register
Figure B.8 Port 5 Block Diagram (P57, P56)* Note: * This diagram is applied to the SCL and SDA pins in the H8/3694N.
Rev.5.00 Nov. 02, 2005 Page 392 of 418 REJ09B0028-0500
Appendix
Internal data bus
RES
SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
WKP
ADTRG
[Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.9 Port 5 Block Diagram (P55)
Rev.5.00 Nov. 02, 2005 Page 393 of 418 REJ09B0028-0500
Appendix
Internal data bus
RES
SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
WKP
[Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.10 Port 5 Block Diagram (P54 to P50)
Rev.5.00 Nov. 02, 2005 Page 394 of 418 REJ09B0028-0500
Appendix
Internal data bus
Timer V OS3 OS2 OS1 OS0
SBY
PDR
PCR
TMOV [Legend] PDR: Port data register PCR: Port control register
Figure B.11 Port 7 Block Diagram (P76)
Rev.5.00 Nov. 02, 2005 Page 395 of 418 REJ09B0028-0500
Appendix
Internal data bus
SBY
PDR
PCR
Timer V TMCIV [Legend] PDR: Port data register PCR: Port control register
Figure B.12 Port 7 Block Diagram (P75)
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Appendix
Internal data bus
SBY
PDR
PCR
Timer V TMRIV [Legend] PDR: Port data register PCR: Port control register
Figure B.13 Port 7 Block Diagram (P74)
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Appendix
Internal data bus
SBY
PDR
PCR
[Legend] PDR: Port data register PCR: Port control register
Figure B.14 Port 8 Block Diagram (P87 to P85)
Rev.5.00 Nov. 02, 2005 Page 398 of 418 REJ09B0028-0500
Appendix
Internal data bus
SBY
Timer W Output control signals A to D PDR
PCR
FTIOA FTIOB FTIOC FTIOD
[Legend] PDR: Port data register PCR: Port control register
Figure B.15 Port 8 Block Diagram (P84 to P81)
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Appendix
Internal data bus
SBY
PDR
PCR
Timer W FTCI [Legend] PDR: Port data register PCR: Port control register
Figure B.16 Port 8 Block Diagram (P80)
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Appendix
Internal data bus
A/D converter
DEC
CH3 to CH0 VIN
Figure B.17 Port B Block Diagram (PB7 to PB0)
B.2
Port
Port States in Each Operating State
Reset High impedance High impedance Sleep Retained Retained Retained Retained Retained High impedance Subsleep Retained Retained Retained Retained Retained High impedance Standby Subactive Active Functioning Functioning Functioning Functioning Functioning High impedance High Functioning impedance*1 High impedance Functioning
P17 to P14, P12 to P10 P22 to P20
P57 to P50*2 High impedance P76 to P74 P87 to P80 PB7 to PB0 High impedance High impedance High impedance
High Functioning 1 impedance* High impedance High impedance High impedance Functioning Functioning High impedance
Notes: 1. High level output when the pull-up MOS is in on state. 2. The P55 to P50 pins are applied to the H8/3694N.
Rev.5.00 Nov. 02, 2005 Page 401 of 418 REJ09B0028-0500
Appendix
Appendix C Product Code Lineup
Product Classification H8/3694 Flash memory Standard version product Product Code Model Marking
HD64F3694H HD64F3694FP HD64F3694FX HD64F3694FY HD64F3694FT HD64F3694H HD64F3694FP HD64F3694FX HD64F3694FY HD64F3694FT
Package Code
QFP-64 (FP-64A) LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48) QFP-64 (FP-64A) LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48) QFP-64 (FP-64A) LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48) QFP-64 (FP-64A)
Product with HD64F3694GH HD64F3694GH POR & LVDC HD64F3694GFP HD64F3694GFP
HD64F3694GFX HD64F3694GFX HD64F3694GFY HD64F3694GFY HD64F3694GFT HD64F3694GFT
Mask ROM version
Standard product
HD6433694H HD6433694FP HD6433694FX HD6433694FY HD6433694FT
HD6433694(***)H HD6433694(***)FP HD6433694(***)FX HD6433694(***)FY HD6433694(***)FT HD6433694G(***)H
Product with HD6433694GH POR & LVDC
HD6433694GFP HD6433694G(***)FP LQFP-64 (FP-64E) HD6433694GFX HD6433694G(***)FX LQFP-48 (FP-48F) HD6433694GFY HD6433694G(***)FY LQFP-48 (FP-48B) HD6433694GFT HD6433694G(***)FT QFN-48(TNP-48)
H8/3693
Mask ROM version
Standard product
HD6433693H HD6433693FP HD6433693FX HD6433693FY HD6433693FT
HD6433693(***)H HD6433693(***)FP HD6433693(***)FX HD6433693(***)FY HD6433693(***)FT
QFP-64 (FP-64A) LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48)
Product with HD6433693GH HD6433693G(***)H QFP-64 (FP-64A) POR & LVDC HD6433693GFP HD6433693G(***)FP LQFP-64 (FP-64E)
HD6433693GFX HD6433693G(***)FX LQFP-48 (FP-48F) HD6433693GFY HD6433693G(***)FY LQFP-48 (FP-48B) HD6433693GFT HD6433693G(***)FT QFN-48(TNP-48)
Rev.5.00 Nov. 02, 2005 Page 402 of 418 REJ09B0028-0500
Appendix
Product Classification H8/3692 Mask ROM version Standard product
Product Code Model Marking
HD6433692H HD6433692FP HD6433692FX HD6433692FY HD6433692FT HD6433692(***)H HD6433692(***)FP HD6433692(***)FX HD6433692(***)FY HD6433692(***)FT HD6433692G(***)H HD6433692G(***)FP HD6433692G(***)FX HD6433692G(***)FY HD6433692G(***)FT HD6433691(***)H HD6433691(***)FP HD6433691(***)FX HD6433691(***)FY HD6433691(***)FT
Package Code
QFP-64 (FP-64A) LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48) QFP-64 (FP-64A) LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48) QFP-64 (FP-64A) LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48) QFP-64 (FP-64A) LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48) QFP-64 (FP-64A) LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48) QFP-64 (FP-64A) LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48)
Product with HD6433692GH POR & LVDC
HD6433692GFP HD6433692GFX HD6433692GFY HD6433692GFT
H8/3691 Mask ROM version
Standard product
HD6433691H HD6433691FP HD6433691FX HD6433691FY HD6433691FT
Product with HD6433691GH HD6433691G(***)H POR & LVDC HD6433691GFP HD6433691G(***)FP
HD6433691GFX HD6433691GFY HD6433691GFT HD6433691G(***)FX HD6433691G(***)FY HD6433691G(***)FT HD6433690(***)H HD6433690(***)FP HD6433690(***)FX HD6433690(***)FY HD6433690(***)FT HD6433690G(***)H HD6433690G(***)FP HD6433690G(***)FX HD6433690G(***)FY HD6433690G(***)FT
H8/3690 Mask ROM version
Standard product
HD6433690H HD6433690FP HD6433690FX HD6433690FY HD6433690FT
Product with HD6433690GH POR & LVDC
HD6433690GFP HD6433690GFX HD6433690GFY HD6433690GFT
Rev.5.00 Nov. 02, 2005 Page 403 of 418 REJ09B0028-0500
Appendix
Product Classification
Product Code Model Marking
Package Code
LQFP-64 (FP-64E)
H8/3694N EEPROM Flash Product with HD64N3694GFP HD64N3694GFP stacked memory POR & LVDC version version Mask ROM version
HD6483694GFP
HD6483694G(***)FP LQFP-64 (FP-64E)
Legend: (***): ROM code. POR & LVDC: Power-on reset and low-voltage detection circuits.
Rev.5.00 Nov. 02, 2005 Page 404 of 418 REJ09B0028-0500
JEITA Package Code P-LQFP64-10x10-0.50 MASS[Typ.] 0.4g
RENESAS Code PLQP0064KC-A
Previous Code FP-64E/FP-64EV
HD
*1
D 33
NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
48
49 bp b1
32
c1 c
E
*2
HE
Terminal cross section
17
Reference Symbol
Dimension in Millimeters Min D E Nom 10 10 A2 HD HE 11.8 11.8 1.45 12.0 12.0 12.2 12.2 Max
64
1
16
ZD
Index mark
ZE
A
A2
c
F
A
1.70
A1
L L1
A1 bp b1
0.00 0.17
0.10 0.22 0.20
0.20 0.27
Appendix D Package Dimensions
The package dimensions that are shown in the Renesas Semiconductor Packages Data Book have priority.
Figure D.1 FP-64E Package Dimensions
Detail F
bp x M c c1 0.12 0.17 0.15
0.22
e
*3
y
e x y ZD ZE L L1
0 0.5
8
0.08 0.10 1.25 1.25 0.3 0.5 1.0 0.7
Appendix
Rev.5.00 Nov. 02, 2005 Page 405 of 418
REJ09B0028-0500
Appendix
c1
E
*2
HE
c
ZE
A
A2
F
c
A1
REJ09B0028-0500
RENESAS Code PRQP0064GB-A Previous Code FP-64A/FP-64AV MASS[Typ.] 1.2g HD
*1
JEITA Package Code P-QFP64-14x14-0.80
D 33
48
NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
49 bp b1
Rev.5.00 Nov. 02, 2005 Page 406 of 418
32
Terminal cross section
17
Reference Symbol
Dimension in Millimeters Min D E A2 HD 16.9 HE A 16.9 Nom 14 14 2.70 17.2 17.2 17.5 17.5 3.05 Max
64
1
16
ZD
Figure D.2 FP-64A Package Dimensions
L L1
A1 bp b1 c
0.00 0.29
0.10 0.37 0.35 0.12 0.17
0.25 0.45
0.22
Detail F
*3
c1
0.15
e y bp x M
e x y ZD ZE L L1
0 0.8
8
0.15 0.10 1.0 1.0 0.5 0.8 1.6 1.1
JEITA Package Code P-LQFP48-10x10-0.65 MASS[Typ.] 0.4g
RENESAS Code PLQP0048JA-A
Previous Code FP-48F/FP-48FV
HD
*1
D 25
36
NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
37
24
bp
E HE
b1
*2
c1
c
48
ZE
13
Reference Symbol
Dimension in Millimeters Min Nom Max
Terminal cross section
D E
10 10 A2 HD HE 11.8 11.8 A 1.45 12.0 12.0 12.2 12.2 1.70
1 Index mark F
12
ZD
A
A2
A1
0.05
0.1
0.15
e bp x y M
*3
A1
Figure D.3 FP-48F Package Dimensions
c
L L1
bp
0.27
0.32
0.37
b1 c c1 0.12
0.30 0.17 0.15 0.22
Detail F
e x y ZD ZE L L1
0 0.65
8
0.13 0.10 1.425 1.425 0.4 0.5 1.0 0.6
Appendix
Rev.5.00 Nov. 02, 2005 Page 407 of 418
REJ09B0028-0500
Appendix
E
*2
HE
c1
c
ZE
A
A2
A1
Figure D.4 FP-48B Package Dimensions
c
REJ09B0028-0500
RENESAS Code PLQP0048KC-A MASS[Typ.] 0.2g Previous Code FP-48B/FP-48BV HD
*1
JEITA Package Code P-LQFP48-7x7-0.50
D 25
36
NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
Rev.5.00 Nov. 02, 2005 Page 408 of 418
24 bp b1 Dimension in Millimeters
Reference Symbol
37
48
13
Min
Nom
Max
Terminal cross section
D E
7 7 A2 HD 8.8 HE A A1 bp 0.03 0.17 0.10 0.22 8.8 1.40 9.0 9.0 9.2 9.2 1.70 0.17 0.27
1
12
ZD F
L L1 x y M
b1 c c1 0.12
0.20 0.17 0.15 0.22
e bp
*3
Detail F
e x y ZD ZE L L1
0 0.5
8
0.08 0.08 0.75 0.75 0.4 0.5 1.0 0.6
JEITA Package Code P-VQFN48-7x7-0.50
RENESAS Code PVQN0048KA-A
Previous Code TNP-48/TNP-48V
MASS[Typ.] 0.1g
HD D 25 24
e ZE
36
37
HE
E
48 13 12 x4 t ZD
Reference Symbol
Dimension in Millimeters Min D Nom 7.0 Max
b b1
xM
Lp
1
E A2 A A1 0.005 b b e
1
7.0 0.90 1.00 0.02 0.17 0.22 0.20 0.5 L x y y t HD HE Z Z c c
1 D E 1 p
0.04 0.27
y1
A2 A
y
A1
Figure D.5 TNP-48 Package Dimensions
c c1
0.23
0.35
0.47 0.05 0.05 0.20 0.20 7.2 7.2 0.75 0.75 0.12 0.17 0.15 0.22
Appendix
Rev.5.00 Nov. 02, 2005 Page 409 of 418
REJ09B0028-0500
Appendix
Appendix E EEPROM Stacked-Structure Cross-Sectional View
Figure E.1 EEPROM Stacked-Structure Cross-Sectional View
Rev.5.00 Nov. 02, 2005 Page 410 of 418 REJ09B0028-0500
Main Revisions and Additions in this Edition
Item Preface Page Revision (See Manual for Details) vi, vii Notes: When using the on-chip emulator (E7, E8) for H8/3694 program development and debugging, the following restrictions must be noted. 1. The NMI pin is reserved for the E7 or E8, and cannot be used. 3. Area H'7000 to H'7FFF is used by the E7 or E8, and is not available to the user. 5. When the E7 or E8 is used, address breaks can be set as either available to the user or for use by the E7 or E8. If address breaks are set as being used by the E7 or E8, the address break control registers must not be accessed. 6. When the E7 or E8 is used, NMI is an input/output pin (open-drain in output mode), P85 and P87 are input pins, and P86 is an output pin. Note has been deleted. Section 1 Overview Figure 1.1 Internal Block Diagram of H8/3694 TM Group of F-ZTAT and Mask-ROM Versions, Figure 1.2 Internal Block Diagram of H8/3694N (EEPROM Stacked Version) 4, 5
Timer V
IIC2
PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7
A/D converter
POR/LVD (optional)
Port B
Data bus (upper)
Address bus
AVCC
Rev.5.00 Nov. 02, 2005 Page 411 of 418 REJ09B0028-0500
Item Section 5 Clock Pulse Generators Figure 5.3 Typical Connection to Crystal Resonator
Figure 5.5 Typical Connection to Ceramic Resonator
Page Revision (See Manual for Details) 70
OSC 1 OSC 2 C2 C1 = C 2 = 10 to 22 pF 2 C1
71
OSC1
C1
C2 OSC2
C1 = 5 to 30 pF C2 = 5 to 30 pF
Section 6 Power-Down Modes 6.1.1 System Control Register 1 (SYSCR1)
76
Bit
Bit Name Description
3
NESEL
Noise Elimination Sampling Frequency Select The subclock pulse generator generates the watch clock signal (W) and the system clock pulse generator generates the oscillator clock (OSC). This bit selects the sampling frequency of the oscillator clock when the watch clock signal (W) is sampled. When OSC = 4 to 20 MHz, clear NESEL to 0.
Section 8 RAM Section 13 Watchdog Timer 13.2.1 Timer Control/Status Register WD (TCSRWD)
107 184
Note: * When the E7 or E8 is used, area H'F780 to H'FB7F must not be accessed.
Bit 4 Bit Name Description TCSRWE Timer Control/Status Register WD Write Enable
Rev.5.00 Nov. 02, 2005 Page 412 of 418 REJ09B0028-0500
Item Section 15 I C Bus Interface 2 (IIC2) 2 15.3.5 I C Bus Status Register (ICSR)
2
Page Revision (See Manual for Details) 242
Bit 3 Bit Name STOP Description Stop Condition Detection Flag [Setting conditions] * * In master mode, when a stop condition is detected after frame transfer In slave mode, when a stop condition is detected after the general call address or the first byte slave address, next to detection of start condition, accords with the address set in SAR
15.7 Usage Notes
264
Added Therefore byte access to ADDR should be done by reading the upper byte first then the lower one. Word access is also possible. ADDR is initialized to H'0000.
Section 16 A/D Converter 268 16.3.1 A/D Data Registers A to D (ADDRA to ADDRD) Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) Figure 18.1 Block Diagram of Power-On Reset Circuit and LowVoltage Detection Circuit Section 21 Electrical Characteristics Table 21.2 DC Characteristics (1) 318 290
RES
CRES
Item Input high voltage
Applicable Symbol Pins VIH PB0 to PB7
Values Test Condition VCC = 4.0 to 5.5 V Min VCC x 0.7 VCC x 0.8
Input low voltage
VIL
RXD,SCL, SDA, P10 to P12, : P80 to P87 PB0 to PB7
VCC = 4.0 to 5.5 V
-0.3
-0.3
Rev.5.00 Nov. 02, 2005 Page 413 of 418 REJ09B0028-0500
Item Table 21.2 DC Characteristics (1)
Page 321
Revision (See Manual for Details)
Mode Active mode 1 Active mode 2 Sleep mode 1 Sleep mode 2 VCC RES Pin VCC Internal State Operates Operates (OSC/64) Only timers operate Only timers operate (OSC/64) Values Test Condition VCC = 4.0 to 5.5 V Min VCC x 0.7 VCC x 0.8 Input low voltage VIL RXD, SCL, SDA P10 to P12, : P80 to P87 PB0 to PB7 RES Pin VCC VCC = 4.0 to 5.5 V -0.3
Table 21.12 DC Characteristics (1)
337
Item Input high voltage Applicable Symbol Pins VIH PB0 to PB7
-0.3
340
Mode Active mode 1 Active mode 2 Sleep mode 1 Sleep mode 2
Internal State Operates Operates (OSC/64)
VCC
Only timers operate Only timers operate (OSC/64)
tSTAH tSCLH
Figure 21.4 I2C Bus Interface Input/Output Timing
352
SCL P* S* tSf
tSCLL
tSCL
Appendix D Package Dimensions
405 to Swapped with new ones. 409
Rev.5.00 Nov. 02, 2005 Page 414 of 418 REJ09B0028-0500
Index
A
A/D converter ......................................... 265 Sample-and-hold circuit...................... 272 Scan mode........................................... 271 Single mode ........................................ 271 Address break ........................................... 63 Addressing modes..................................... 34 Absolute address................................... 36 Immediate ............................................. 36 Memory indirect ................................... 37 Program-counter relative ...................... 36 Register direct....................................... 35 Register indirect.................................... 35 Register indirect with displacement...... 35 Register indirect with post-increment... 35 Register indirect with pre-decrement.... 36 Random address read .......................... 286 Sequential read.................................... 286 Slave address reference register (ESAR)................................................ 281 Slave addressing.................................. 281 Start condition..................................... 280 Stop condition ..................................... 281 Effective address....................................... 38 Effective address extension....................... 33 Exception handling ................................... 49 Reset exception handling ...................... 56 Trap instruction..................................... 49
F
Flash memory ........................................... 87 Boot mode............................................. 93 Boot program ........................................ 93 Erase/erase-verify ............................... 100 Erasing units ......................................... 87 Error protection................................... 103 Hardware protection............................ 103 Power-down state................................ 104 Program/program-verify ....................... 98 Programmer mode............................... 104 Programming units................................ 87 Programming/erasing in user program mode ....................................... 96 Software protection............................. 103
C
Clock pulse generators.............................. 69 Prescaler S ............................................ 73 Prescaler W........................................... 73 Subclock generator ............................... 72 System clock generator......................... 70 Condition field.......................................... 33 Condition-code register (CCR)................. 19 CPU .......................................................... 13
E
EEPROM................................................ 277 Acknowledge ...................................... 281 Acknowledge polling.......................... 284 Byte write ........................................... 283 Current address read ........................... 285 EEPROM interface ............................. 280 Page write ........................................... 283
G
General registers ....................................... 18
I
I/O ports .................................................. 109
Rev.5.00 Nov. 02, 2005 Page 415 of 418 REJ09B0028-0500
I/O port block diagrams ...................... 385 I2C bus data format ................................. 246 I2C bus interface 2 (IIC2) ....................... 231 Acknowledge...................................... 247 Bit synchronous circuit....................... 263 Clocked synchronous serial format..... 255 Noise canceler .................................... 257 Slave address ...................................... 246 Start condition .................................... 246 Stop condition..................................... 247 Transfer rate........................................ 235 Instruction set ........................................... 24 Arithmetic operations instructions........ 26 Bit Manipulation instructions ............... 29 Block data transfer instructions ............ 33 Branch instructions ............................... 31 Data transfer instructions...................... 25 Logic operations instructions................ 28 Shift instructions................................... 28 System control instructions................... 32 Internal power supply stepdown circuit ............................................ 299 Interrupt Internal interrupts ................................. 58 Interrupt response time ......................... 60 IRQ3 to IRQ0 interrupts ....................... 57 NMI interrupt........................................ 57 WKP5 to WKP0 interrupts ................... 57 Interrupt mask bit (I)................................. 19
M
Memory map............................................. 14 Module standby function .......................... 86
O
On-board programming modes ................. 93 Operation field .......................................... 33
P
Package ....................................................... 3 Package dimensions................................ 405 Pin arrangement .......................................... 6 Power-down modes................................... 75 Sleep mode............................................ 83 Standby mode ....................................... 83 Subactive mode..................................... 84 Subsleep mode ...................................... 83 Power-on reset ........................................ 289 Power-on reset circuit ............................. 293 Product code lineup ................................ 402 Program counter (PC) ............................... 19
R
Register ABRKCR...................... 64, 304, 309, 312 ABRKSR ...................... 65, 304, 309, 312 ADCR ......................... 270, 304, 308, 312 ADCSR ....................... 269, 304, 308, 312 ADDRA ...................... 268, 303, 308, 312 ADDRB ...................... 268, 304, 308, 312 ADDRC ...................... 268, 304, 308, 312 ADDRD ...................... 268, 304, 308, 312 BARH ........................... 66, 304, 309, 312 BARL............................ 66, 304, 309, 312 BDRH ........................... 66, 304, 309, 312 BDRL............................ 66, 304, 309, 312 BRR ............................ 198, 303, 308, 312
L
Large current ports...................................... 2 Low-voltage detection circuit ................. 289 LVDI ...................................................... 295 LVDI (interrupt by low voltage detect) circuit...................................................... 295 LVDR ..................................................... 294 LVDR (reset by low voltage detect) circuit .......................................... 294
Rev.5.00 Nov. 02, 2005 Page 416 of 418 REJ09B0028-0500
EBR1 ............................ 91, 303, 308, 311 EKR ............................ 279, 306, 310, 313 FENR............................ 92, 303, 308, 311 FLMCR1....................... 89, 303, 308, 311 FLMCR2....................... 90, 303, 308, 311 FLPWCR ...................... 92, 303, 308, 311 GRA............................ 165, 302, 307, 311 GRB............................ 165, 303, 307, 311 GRC............................ 165, 303, 307, 311 GRD............................ 165, 303, 307, 311 ICCR1......................... 234, 302, 307, 311 ICCR2......................... 236, 302, 307, 311 ICDRR........................ 245, 302, 307, 311 ICDRS ................................................ 245 ICDRT ........................ 245, 302, 307, 311 ICIER.......................... 239, 302, 307, 311 ICMR.......................... 237, 302, 307, 311 ICSR ........................... 241, 302, 307, 311 IEGR1........................... 51, 306, 309, 313 IEGR2........................... 52, 306, 309, 313 IENR1........................... 53, 306, 309, 313 IRR1 ............................. 54, 306, 309, 313 IWPR ............................ 55, 306, 309, 313 LVDCR....................... 290, 302, 307, 311 LVDSR ....................... 292, 302, 307, 311 MSTCR1....................... 79, 306, 309, 313 PCR1........................... 111, 305, 309, 313 PCR2........................... 115, 305, 309, 313 PCR5........................... 119, 305, 309, 313 PCR7........................... 124, 305, 309, 313 PCR8........................... 126, 305, 309, 313 PDR1 .......................... 111, 305, 309, 312 PDR2 .......................... 115, 305, 309, 312 PDR5 .......................... 119, 305, 309, 312 PDR7 .......................... 124, 305, 309, 312 PDR8 .......................... 127, 305, 309, 312 PDRB.......................... 130, 305, 309, 312 PMR1.......................... 110, 305, 309, 313 PMR5.......................... 118, 305, 309, 313 PUCR1........................ 112, 305, 309, 312
PUCR5 ........................ 120, 305, 309, 312 RDR ............................ 192, 303, 308, 312 RSR..................................................... 192 SAR............................. 244, 302, 307, 311 SCR3........................... 194, 303, 308, 312 SMR ............................ 193, 303, 308, 312 SSR ............................. 196, 303, 308, 312 SYSCR1........................ 76, 306, 309, 313 SYSCR2........................ 78, 306, 309, 313 TCA ............................ 134, 303, 308, 312 TCNT .......................... 164, 302, 307, 311 TCNTV ....................... 139, 303, 308, 312 TCORA....................... 139, 303, 308, 311 TCORB ....................... 139, 303, 308, 311 TCRV0........................ 140, 303, 308, 311 TCRV1........................ 143, 303, 308, 312 TCRW......................... 158, 302, 307, 311 TCSRV........................ 142, 303, 308, 311 TCSRWD.................... 184, 304, 308, 312 TCWD......................... 185, 304, 308, 312 TDR ............................ 192, 303, 308, 312 TIERW........................ 159, 302, 307, 311 TIOR0 ......................... 161, 302, 307, 311 TIOR1 ......................... 163, 302, 307, 311 TMA............................ 133, 303, 308, 312 TMRW ........................ 157, 302, 307, 311 TMWD........................ 186, 304, 309, 312 TSR ..................................................... 192 TSRW ......................... 160, 302, 307, 311 Register field............................................. 33
S
Serial communication interface 3 (SCI3) ..................................................... 189 Asynchronous mode............................ 205 Bit rate................................................. 198 Break................................................... 229 Clocked synchronous mode ................ 213 Framing error ...................................... 209
Rev.5.00 Nov. 02, 2005 Page 417 of 418 REJ09B0028-0500
Mark state ........................................... 229 Multiprocessor communication function............................................... 221 Overrun error ...................................... 209 Parity error.......................................... 209 Stacked-structure cross sectional view of H8/3694N .................................. 410 Stack pointer (SP)..................................... 19
Timer V................................................... 137 Timer W.................................................. 153
V
Vector address........................................... 49
W T
Timer A .................................................. 131 Watchdog timer....................................... 183
Rev.5.00 Nov. 02, 2005 Page 418 of 418 REJ09B0028-0500
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/3694 Group
Publication Date: 1st Edition, Jul, 2001 Rev.5.00, Nov. 02, 2005 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.
2005. Renesas Technology Corp. All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> 2-796-3115, Fax: <82> 2-796-2145
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